Hi Niklas,
On Tue, Jun 25, 2024 at 3:31 PM Niklas Söderlund
<niklas.soderlund+renesas@xxxxxxxxxxxx> wrote:
> Align with other Renesas SoCs and use the specific compatible for the
> PHYs connected to AVB1 and AVB2, Marvell 88Q2110/QFN40. This allows
> software to identify the PHY model at any time, regardless of the state
> of the PHY reset line.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi
> +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi
> @@ -27,7 +27,8 @@ mdio {
> reset-post-delay-us = <4000>;
>
> avb1_phy: ethernet-phy@0 {
> - compatible = "ethernet-phy-ieee802.3-c45";
> + compatible = "ethernet-phy-id002b.0980",
> + "ethernet-phy-ieee802.3-c22";
> reg = <0>;
> interrupt-parent = <&gpio6>;
> interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> @@ -49,7 +50,8 @@ mdio {
> reset-post-delay-us = <4000>;
>
> avb2_phy: ethernet-phy@0 {
> - compatible = "ethernet-phy-ieee802.3-c45";
> + compatible = "ethernet-phy-id002b.0980",
> + "ethernet-phy-ieee802.3-c22";
> reg = <0>;
> interrupt-parent = <&gpio5>;
> interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
Originally, I added explicit ethernet-phy-id* compatible values because
Linux does not deassert the reset line before trying to read the PHY
ID, hence failing. Have you checked if this is still the case after
introducing the mdio subnode? I'd rather not add the explicit IDs,
as board manufacturers may change the PHY revision or even the PHY
model without notice.
You can find my original test procedure, using kexec or bind/rebind, at
https://lore.kernel.org/cover.1631174218.git.geert+renesas@xxxxxxxxx/.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
