This series adds support for the AP sub-system clock controller in the T-Head TH1520 [1]. Yangtao Li originally submitted this series in May 2023 [2]. Jisheng made additional improvements and then passed on the work in progress to me. Changes in v2: - Add clock property to the gpio nodes after Conor asked why they were missing. These clock gates correspond to enable bits in PERI_CLK_CFG. - Drop 2 cell address and size properties from the binding example per Conor and add Reviewed-by from from Conor. Changes in v1: - Split th1520_clks into groups for gate, mux, div, pll - Convert gate clocks to devm_clk_hw_register_gate_parent_data() - Convert mux clocks to devm_clk_hw_register_mux_parent_data_table() - Split the PLL recalculation into th1520_pll_vco_recalc_rate() and th1520_pll_postdiv_recalc_rate(). Based on Emil's comments in v1, add logic to handle the fractional portion of feedback divide value when the delta-sigma modulator (DSM) is active. - Drop clock-names from the binding per Stephan to avoid relying on anything other than the cell index when describing clk_parent_data (note: I dropped Rob's Rb because I changed the binding patch) - Rename reg/reg2 to cfg0/cfg1 to match the SoC documentation - Rename struct for pll clocks from ccu_mdiv to ccu_pll - Rebase on v6.10-rc3, remove the dts node reordering patch from v3 now that it is in mainline Changes in RFC v3 [3]: - Drop redundant new line and unused clk label from the dts example in the DT binding which I failed to fix in v2. - Add patch [4] from Thomas Bonnefille that fixes dts node ordering in th1520.dtsi. Conor has already merged it into riscv-dt-for-next so the dts patches in this series are based on top of that. - Remove fixed uart clock and converted uart DT nodes to use clocks from the clock controller. - Remove fixed apb clock and converted the dma controller and timer DT nodes to use a clock from the clock controller. - Made ccu_disable_helper() and ccu_enable_helper() to static functions - Follow the advice from Stephen Boyd in Yangtao's original series to not use strings for clk tree topology. Created clk_parent_data arrays to be used with CLK_HW_INIT_PARENTS_DATA instead of parent strings. - Rebase on top of v6.9-rc7 Changes in RFC v2 [5]: - squash the header file patch into the DT schema patch - describe the changes I made to original series in the cover letter instead of the individual patches - fix my typo in my email address Changes in RFC v1 [6] from the original series: - corrected the npu_clk enable bit - deduplicated CLK_NPU and CLK_NPU_AXI number in header - fixed c910_i0_clk reg typo - fixed checkpatch and dt_binding_check warnings - rebased on v6.9-rc5 - revised commit descriptions Thank you, Drew [1] https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [2] https://lore.kernel.org/all/20230515054402.27633-1-frank.li@xxxxxxxx/ [3] https://lore.kernel.org/all/20240506-th1520-clk-v3-0-085a18a23a7f@xxxxxxxxxxxxxxx/ [4] https://lore.kernel.org/all/20240425082138.374445-1-thomas.bonnefille@xxxxxxxxxxx/ [5] https://lore.kernel.org/all/20240426-th1520-clk-v2-v2-0-96b829e6fcee@xxxxxxxxxxxxxxx/ [6] https://lore.kernel.org/all/20240110-clk-th1520-v1-0-8b0682567984@xxxxxxxxxxxxxxx/ To: Jisheng Zhang <jszhang@xxxxxxxxxx> To: Guo Ren <guoren@xxxxxxxxxx> To: Fu Wei <wefu@xxxxxxxxxx> To: Yangtao Li <frank.li@xxxxxxxx> To: Thomas Bonnefille <thomas.bonnefille@xxxxxxxxxxx> To: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> To: Michael Turquette <mturquette@xxxxxxxxxxxx> To: Stephen Boyd <sboyd@xxxxxxxxxx> To: Rob Herring <robh@xxxxxxxxxx> To: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx> To: Conor Dooley <conor+dt@xxxxxxxxxx> To: Paul Walmsley <paul.walmsley@xxxxxxxxxx> To: Palmer Dabbelt <palmer@xxxxxxxxxxx> To: Albert Ou <aou@xxxxxxxxxxxxxxxxx> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx Cc: linux-clk@xxxxxxxxxxxxxxx Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-kernel@xxxxxxxxxxxxxxx Signed-off-by: Drew Fustini <dfustini@xxxxxxxxxxxxxxx> --- Drew Fustini (7): dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller riscv: dts: thead: change TH1520 uart nodes to use clock controller riscv: dts: thead: change TH1520 mmc nodes to use clock controller riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller riscv: dts: thead: add clock to TH1520 gpio nodes .../bindings/clock/thead,th1520-clk-ap.yaml | 53 + MAINTAINERS | 3 + arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 12 - .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 12 - arch/riscv/boot/dts/thead/th1520.dtsi | 73 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 12 + drivers/clk/thead/Makefile | 2 + drivers/clk/thead/clk-th1520-ap.c | 1086 ++++++++++++++++++++ include/dt-bindings/clock/thead,th1520-clk-ap.h | 96 ++ 11 files changed, 1290 insertions(+), 61 deletions(-) --- base-commit: 83a7eefedc9b56fe7bfeff13b6c7356688ffa670 change-id: 20240622-th1520-clk-e813a97b9e16 Best regards, -- Drew Fustini <dfustini@xxxxxxxxxxxxxxx>
