Add device tree binding Documentation details for Qualcomm SM4250 LPASS LPI(Low power Island) pinctrl device. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx> --- .../pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..9612e21183fa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM4250 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC. + +properties: + compatible: + const: qcom,sm4250-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm4250-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm4250-lpass-state" + additionalProperties: false + +$defs: + qcom-sm4250-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-6])$" + + function: + enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, + dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a, + ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws, + i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk, + swr_wsa_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + lpi_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm4250-lpass-lpi-pinctrl"; + reg = <0xa7c0000 0x20000>, + <0xa950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 19>; + + i2s2-active-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + i2s2-sleep-clk-state { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; -- 2.25.1
