On Fri, Jun 21, 2024 at 04:22:31PM +0800, Minda Chen wrote: > Add PCIe dts configuraion for JH7110 SoC platform. I think the commit message should mention that the star64 doesn't have a pci port exposed. If nothing else crops up, I'll edit it myself if that's okay? Thanks, Conor. > > Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> > Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > --- > .../boot/dts/starfive/jh7110-common.dtsi | 62 +++++++++++++ > .../boot/dts/starfive/jh7110-milkv-mars.dts | 7 ++ > .../jh7110-starfive-visionfive-2.dtsi | 8 ++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > 4 files changed, 163 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > index 8ff6ea64f048..f91abc660ae8 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > @@ -294,6 +294,20 @@ > status = "okay"; > }; > > +&pcie0 { > + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > + phys = <&pciephy0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie0_pins>; > +}; > + > +&pcie1 { > + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > + phys = <&pciephy1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie1_pins>; > +}; > + > &pwmdac { > pinctrl-names = "default"; > pinctrl-0 = <&pwmdac_pins>; > @@ -476,6 +490,54 @@ > }; > }; > > + pcie0_pins: pcie0-0 { > + clkreq-pins { > + pinmux = <GPIOMUX(27, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_NONE)>; > + bias-pull-down; > + drive-strength = <2>; > + input-enable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + > + wake-pins { > + pinmux = <GPIOMUX(32, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_NONE)>; > + bias-pull-up; > + drive-strength = <2>; > + input-enable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + }; > + > + pcie1_pins: pcie1-0 { > + clkreq-pins { > + pinmux = <GPIOMUX(29, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_NONE)>; > + bias-pull-down; > + drive-strength = <2>; > + input-enable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + > + wake-pins { > + pinmux = <GPIOMUX(21, GPOUT_LOW, > + GPOEN_DISABLE, > + GPI_NONE)>; > + bias-pull-up; > + drive-strength = <2>; > + input-enable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + }; > + > pwmdac_pins: pwmdac-0 { > pwmdac-pins { > pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts > index fa0eac78e0ba..5cb9e99e1dac 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts > @@ -17,6 +17,13 @@ > assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; > }; > > +&pcie0 { > + status = "okay"; > +}; > + > +&pcie1 { > + status = "okay"; > +}; > > &phy0 { > motorcomm,tx-clk-adj-enabled; > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 9d70f21c86fc..18f38fc790a4 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -32,3 +32,11 @@ > &mmc0 { > non-removable; > }; > + > +&pcie0 { > + status = "okay"; > +}; > + > +&pcie1 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 18047195c600..5ac70759e0ab 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -1214,5 +1214,91 @@ > #reset-cells = <1>; > power-domains = <&pwrc JH7110_PD_VOUT>; > }; > + > + pcie0: pcie@940000000 { > + compatible = "starfive,jh7110-pcie"; > + reg = <0x9 0x40000000 0x0 0x1000000>, > + <0x0 0x2b000000 0x0 0x100000>; > + reg-names = "cfg", "apb"; > + linux,pci-domain = <0>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, > + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; > + interrupts = <56>; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, > + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, > + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, > + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; > + msi-controller; > + device_type = "pci"; > + starfive,stg-syscon = <&stg_syscon>; > + bus-range = <0x0 0xff>; > + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, > + <&stgcrg JH7110_STGCLK_PCIE0_TL>, > + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, > + <&stgcrg JH7110_STGCLK_PCIE0_APB>; > + clock-names = "noc", "tl", "axi_mst0", "apb"; > + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, > + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, > + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, > + <&stgcrg JH7110_STGRST_PCIE0_BRG>, > + <&stgcrg JH7110_STGRST_PCIE0_CORE>, > + <&stgcrg JH7110_STGRST_PCIE0_APB>; > + reset-names = "mst0", "slv0", "slv", "brg", > + "core", "apb"; > + status = "disabled"; > + > + pcie_intc0: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > + > + pcie1: pcie@9c0000000 { > + compatible = "starfive,jh7110-pcie"; > + reg = <0x9 0xc0000000 0x0 0x1000000>, > + <0x0 0x2c000000 0x0 0x100000>; > + reg-names = "cfg", "apb"; > + linux,pci-domain = <1>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, > + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; > + interrupts = <57>; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, > + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, > + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, > + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; > + msi-controller; > + device_type = "pci"; > + starfive,stg-syscon = <&stg_syscon>; > + bus-range = <0x0 0xff>; > + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, > + <&stgcrg JH7110_STGCLK_PCIE1_TL>, > + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, > + <&stgcrg JH7110_STGCLK_PCIE1_APB>; > + clock-names = "noc", "tl", "axi_mst0", "apb"; > + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, > + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, > + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, > + <&stgcrg JH7110_STGRST_PCIE1_BRG>, > + <&stgcrg JH7110_STGRST_PCIE1_CORE>, > + <&stgcrg JH7110_STGRST_PCIE1_APB>; > + reset-names = "mst0", "slv0", "slv", "brg", > + "core", "apb"; > + status = "disabled"; > + > + pcie_intc1: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > }; > }; > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
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