On Fri, Jun 21, 2024 at 04:48:50PM +0200, Lorenzo Bianconi wrote: > Introduce support for Airoha EN7581 pcie controller to mediatek-gen3 > pcie controller driver. s/pcie/PCIe/ (twice) > Tested-by: Zhengping Zhang <zhengping.zhang@xxxxxxxxxx> > Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> > --- > drivers/pci/controller/Kconfig | 2 +- > drivers/pci/controller/pcie-mediatek-gen3.c | 84 ++++++++++++++++++++- > 2 files changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig > index e534c02ee34f..3bd6c9430010 100644 > --- a/drivers/pci/controller/Kconfig > +++ b/drivers/pci/controller/Kconfig > @@ -196,7 +196,7 @@ config PCIE_MEDIATEK > > config PCIE_MEDIATEK_GEN3 > tristate "MediaTek Gen3 PCIe controller" > - depends on ARCH_MEDIATEK || COMPILE_TEST > + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST > depends on PCI_MSI > help > Adds support for PCIe Gen3 MAC controller for MediaTek SoCs. > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index 9842617795a9..2dacfed665c6 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -7,6 +7,7 @@ > */ > > #include <linux/clk.h> > +#include <linux/clk-provider.h> > #include <linux/delay.h> > #include <linux/iopoll.h> > #include <linux/irq.h> > @@ -21,6 +22,8 @@ > #include <linux/pm_domain.h> > #include <linux/pm_runtime.h> > #include <linux/reset.h> > +#include <linux/of_pci.h> > +#include <linux/of_device.h> Existing list of includes is sorted. Preserve that sorted order. > +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > +{ > + struct device *dev = pcie->dev; > + int err; > + > + writel_relaxed(0x23020133, pcie->base + 0x10044); > + writel_relaxed(0x50500032, pcie->base + 0x15030); > + writel_relaxed(0x50500032, pcie->base + 0x15130); Magic. Needs #defines at least for the registers. These offsets are HUGE, far bigger than the existing offsets: #define PCIE_CFGNUM_REG 0x140 #define PCIE_CFG_OFFSET_ADDR 0x1000 #define PCIE_TRANS_TABLE_BASE_REG 0x800 #define PCIE_MSI_SET_BASE_REG 0xc00 #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 #define PCIE_MSI_SET_ENABLE_REG 0x190 #define PCIE_INT_ENABLE_REG 0x180 #define PCIE_SETTING_REG 0x80 #define PCIE_PCI_IDS_1 0x9c #define PCIE_MISC_CTRL_REG 0x348 #define PCIE_RST_CTRL_REG 0x148 #define PCIE_LINK_STATUS_REG 0x154 #define PCIE_LTSSM_STATUS_REG 0x150 #define PCIE_INT_STATUS_REG 0x184 > + err = phy_init(pcie->phy); > + if (err) { > + dev_err(dev, "failed to initialize PHY\n"); > + return err; > + } > + mdelay(30); Source? Cite the spec that requires this delay and add a #define if possible. > + err = phy_power_on(pcie->phy); > + if (err) { > + dev_err(dev, "failed to power on PHY\n"); > + goto err_phy_on; > + } > + > + err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts, > + pcie->phy_resets); > + if (err) { > + dev_err(dev, "failed to deassert PHYs\n"); > + goto err_phy_deassert; > + } > + usleep_range(5000, 10000); Source? > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > + err = clk_bulk_prepare(pcie->num_clks, pcie->clks); > + if (err) { > + dev_err(dev, "failed to prepare clock\n"); > + goto err_clk_prepare; > + } > + > + writel_relaxed(0x41474147, pcie->base + PCIE_EQ_PRESET_01_REF); > + writel_relaxed(0x1018020f, pcie->base + PCIE_PIPE4_PIE8_REG); > + mdelay(10); Source?