On 19/06/2024 16:57, Detlev Casanova wrote:
> Add the rkvdec2 Video Decoder to the RK3588s devicetree.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 50 +++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 6ac5ac8b48ab..7690632f57f1 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -2596,6 +2596,16 @@ system_sram2: sram@ff001000 {
> ranges = <0x0 0x0 0xff001000 0xef000>;
> #address-cells = <1>;
> #size-cells = <1>;
> +
> + vdec0_sram: rkvdec-sram@0 {
> + reg = <0x0 0x78000>;
> + pool;
> + };
> +
> + vdec1_sram: rkvdec-sram@1 {
> + reg = <0x78000 0x77000>;
> + pool;
> + };
> };
>
> pinctrl: pinctrl {
> @@ -2665,6 +2675,46 @@ gpio4: gpio@fec50000 {
> #interrupt-cells = <2>;
> };
> };
> +
> + vdec0: video-decoder@fdc38100 {
> + compatible = "rockchip,rk3588-vdec";
> + reg = <0x0 0xfdc38100 0x0 0x500>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
> + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
> + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
> + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
> + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
> + assigned-clock-rates = <800000000>, <600000000>,
> + <600000000>, <1000000000>;
> + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
> + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
> + reset-names = "rst_axi", "rst_ahb", "rst_cabac",
> + "rst_core", "rst_hevc_cabac";
> + power-domains = <&power RK3588_PD_RKVDEC0>;
> + sram = <&vdec0_sram>;
> + status = "okay";
Should not be needed. Where did you disable it?
> + };
> +
> + vdec1: video-decoder@fdc40100 {
> + compatible = "rockchip,rk3588-vdec";
> + reg = <0x0 0xfdc40100 0x0 0x500>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
> + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
> + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
> + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
> + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
> + assigned-clock-rates = <800000000>, <600000000>,
> + <600000000>, <1000000000>;
> + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
> + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
> + reset-names = "rst_axi", "rst_ahb", "rst_cabac",
> + "rst_core", "rst_hevc_cabac";
> + power-domains = <&power RK3588_PD_RKVDEC1>;
> + sram = <&vdec1_sram>;
> + status = "okay";
Should not be needed. Where did you disable it?
Best regards,
Krzysztof
