Hi Matthias, On 19/06/24 4:54 pm, Matthias Schiffer wrote: > Add PRU Ethernet controller and PHY nodes, as it was previously done for > the AM64x EVM Device Trees. > > Differing from the EVM, we add the virtual ethernet controller device > below &icssg1 instead of the top level. Besides being slighly more > accurate, this has the advantage that the node is implicitly disabled > when &icssg1 has status = "disabled" (which the TQMa64xxL bootloader > adds as a fixup when running on an AM64x variant without ICSSG support), > thus avoiding leaving the ethernet device in EPROBE_DEFER limbo forever. > > Signed-off-by: Matthias Schiffer <matthias.schiffer@xxxxxxxxxxxxxxx> > --- > > k3-am642-evm.dts uses "ti-pruss/am64x-sr2-*" filenames instead of > "ti-pruss/am65x-sr2-*", however it is not clear to me where these would > come from - I'm not aware of any firmwares named like that. > During upstreaming of icssg1-eth node in "k3-am642-evm.dts", it was raised that the firmware name should be am64x-sr2* instead of am65x-sr2* [1] > So far, these firmwares are not in mainline linux-firmware; TI's > reference BSPs include firmware from ti-linux-firmware [1], and the same > "am65x-sr2" firmwares are used on AM65x and AM64x SoCs. > Yes currently the firmware used for both AM65x and AM64x is am65x-sr2*, but that firmware name is not taken from device tree. It is directly encoded in the driver. Plan is to have different firmware for both SoCs in future and when that happens driver will read the firmware name from device tree. For that case, the firmware name here is "am64x-sr2*" [1] https://lore.kernel.org/all/20231207134343.ufiy2owik5kn3y2r@degrease/ > [1] https://git.ti.com/gitweb?p=processor-firmware/ti-linux-firmware.git;a=tree;f=ti-pruss;h=a220bdc6dce5e11845b5c6337ff9b2d329aee196;hb=refs/heads/ti-linux-firmware > > .../dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 100 ++++++++++++++++++ > 1 file changed, 100 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts > index 1f4dc5ad1696a..0eff392a29b00 100644 > --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts > +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts > @@ -24,6 +24,8 @@ / { > > aliases { > ethernet0 = &cpsw_port1; > + ethernet1 = &icssg1_emac0; > + ethernet2 = &icssg1_emac1; > i2c1 = &mcu_i2c0; > mmc1 = &sdhci1; > serial0 = &mcu_uart0; > @@ -154,6 +156,104 @@ &epwm5 { > status = "okay"; > }; > > +&icssg1 { > + icssg1_eth: ethernet { > + compatible = "ti,am642-icssg-prueth"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pru_icssg1_rgmii1_pins>, <&pru_icssg1_rgmii2_pins>; > + interrupt-parent = <&icssg1_intc>; > + interrupts = <24 0 2>, <25 1 3>; > + interrupt-names = "tx_ts0", "tx_ts1"; > + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ > + <&main_pktdma 0xc201 15>, /* egress slice 0 */ > + <&main_pktdma 0xc202 15>, /* egress slice 0 */ > + <&main_pktdma 0xc203 15>, /* egress slice 0 */ > + <&main_pktdma 0xc204 15>, /* egress slice 1 */ > + <&main_pktdma 0xc205 15>, /* egress slice 1 */ > + <&main_pktdma 0xc206 15>, /* egress slice 1 */ > + <&main_pktdma 0xc207 15>, /* egress slice 1 */ > + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ > + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ > + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", > + "tx1-0", "tx1-1", "tx1-2", "tx1-3", > + "rx0", "rx1"; > + sram = <&oc_sram>; > + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", > + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", > + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; > + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; > + ti,pruss-gp-mux-sel = <2>, /* MII mode */ > + <2>, > + <2>, > + <2>, /* MII mode */ > + <2>, > + <2>; > + ti,mii-g-rt = <&icssg1_mii_g_rt>; > + ti,mii-rt = <&icssg1_mii_rt>; > + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; > + > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + icssg1_emac0: port@0 { > + reg = <0>; > + phy-handle = <&icssg1_phy0c>; > + phy-mode = "rgmii-id"; > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + }; > + > + icssg1_emac1: port@1 { > + reg = <1>; > + phy-handle = <&icssg1_phy03>; > + phy-mode = "rgmii-id"; > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + }; > + }; > + }; > +}; > + > +&icssg1_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&pru_icssg1_mdio_pins>; > + status = "okay"; > + > + /* phy-mode is fixed up to rgmii-rxid by prueth driver to account for > + * the SoC integration, so the only rx-internal-delay and no > + * tx-internal-delay is set for the PHYs. > + */ > + > + icssg1_phy03: ethernet-phy@3 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0x3>; > + reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; > + reset-assert-us = <1000>; > + reset-deassert-us = <1000>; > + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; > + }; > + > + icssg1_phy0c: ethernet-phy@c { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0xc>; > + reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>; > + reset-assert-us = <1000>; > + reset-deassert-us = <1000>; > + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; > + }; > +}; > + > + > &main_gpio0 { > pinctrl-names = "default"; > pinctrl-0 = <&main_gpio0_digital_pins>, -- Thanks and Regards, Danish
