On 06/19, David Lechner wrote: > On 6/18/24 6:10 PM, Marcelo Schmitt wrote: > > > > + > > +MOSI idle state configuration > > +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > + > > +Common SPI protocol implementations don't specify any state or behavior for the > > +MOSI line when the controller is not clocking out data. However, there do exist > > +peripherals that require specific MOSI line state when data is not being clocked > > +out. For example, if the peripheral expects the MOSI line to be high when the > > +controller is not clocking out data (SPI_MOSI_IDLE_HIGH), then a transfer in SPI > > +mode 0 would look like the following: > > + > > +:: > > + > > + nCSx ___ ___ > > + \_________________________________________________________________/ > > + • • > > + • • > > + SCLK ___ ___ ___ ___ ___ ___ ___ ___ > > + _______/ \___/ \___/ \___/ \___/ \___/ \___/ \___/ \_____ > > + • : ; : ; : ; : ; : ; : ; : ; : ; • > > + • : ; : ; : ; : ; : ; : ; : ; : ; • > > + MOSI _____ _______ _______ _______________ ___ > > + 0x56 \_0_____/ 1 \_0_____/ 1 \_0_____/ 1 1 \_0_____/ > > + • ; ; ; ; ; ; ; ; • > > + • ; ; ; ; ; ; ; ; • > > + MISO XXX__________ _______________________ _______ XXX > > + 0xBA XXX__/ 1 \_____0_/ 1 1 1 \_____0__/ 1 \____0__XXX > > + > > +Legend:: > > + > > + • marks the start/end of transmission; > > + : marks when data is clocked into the peripheral; > > + ; marks when data is clocked into the controller; > > + X marks when line states are not specified. > > + > > +In this extension to the usual SPI protocol, the MOSI line state is specified to > > +be kept high when CS is active but the controller is not clocking out data to > > I think it would be less ambiguous to say "asserted" instead of "active". I'm not sure. IMHO, it looks less ambiguous to say a CS is active. I think the most common for CS lines is to have a CS that is active low (i.e. the line is at a low voltage level when the controller is selecting the device). To me, "assert" sounds closer to the idea o setting something (like a bit to 1), which is the opposite of active low CS. Though, no strong opinion about it. I go with what the maintainers prefer. > > > +the peripheral and also when CS is inactive. > > As I mentioned in a previous review, I think the key detail here is that the > MOSI line has to be in the required state during the CS line assertion > (falling edge). I didn't really get that from the current wording. The current > wording makes it sound like MOSI needs to be high indefinitely longer. It may be that we only need MOSI high just before bringing CS low. Though, I don't see that info in the datasheets. How much time would MOSI be required to be high prior to bringing CS low? The timing diagrams for register access and ADC sampling in "3-wire" mode all start and end with MOSI at logical 1 (high). I think reg access work if MOSI is brought low after CS gets low, but sample read definitely don't work.
