Hi Inochi, > From: Inochi Amaoto <inochiama@xxxxxxxxxxx> > Sent: Wednesday, 19 June 2024 06:33 > To: Yuntao Dai <d1581209858@xxxxxxxx>; jassisinghbrar@xxxxxxxxx <jassisinghbrar@xxxxxxxxx>; robh@xxxxxxxxxx <robh@xxxxxxxxxx>; krzk+dt@xxxxxxxxxx <krzk+dt@xxxxxxxxxx>; conor+dt@xxxxxxxxxx <conor+dt@xxxxxxxxxx>; unicorn_wang@xxxxxxxxxxx <unicorn_wang@xxxxxxxxxxx>; inochiama@xxxxxxxxxxx <inochiama@xxxxxxxxxxx>; paul.walmsley@xxxxxxxxxx <paul.walmsley@xxxxxxxxxx>; palmer@xxxxxxxxxxx <palmer@xxxxxxxxxxx>; aou@xxxxxxxxxxxxxxxxx <aou@xxxxxxxxxxxxxxxxx> > Cc: linux-kernel@xxxxxxxxxxxxxxx <linux-kernel@xxxxxxxxxxxxxxx>; devicetree@xxxxxxxxxxxxxxx <devicetree@xxxxxxxxxxxxxxx>; linux-riscv@xxxxxxxxxxxxxxxxxxx <linux-riscv@xxxxxxxxxxxxxxxxxxx> > Subject: Re: [PATCH 1/3] dt-bindings: mailbox: add Sophgo cv18x SoCs mailbox > > On Tue, Jun 18, 2024 at 11:12:33PM GMT, Yuntao Dai wrote: > > Add devicetree bindings documentation for Sophgo cv18x SoCs mailbox > > > > Signed-off-by: Yuntao Dai <d1581209858@xxxxxxxx> > > --- > > .../mailbox/sophgo,cv1800b-mailbox.yaml | 75 +++++++++++++++++++ > > 1 file changed, 75 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > > > diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > new file mode 100644 > > index 000000000..e1868aaf2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml > > @@ -0,0 +1,75 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sophgo cv1800b mailbox controller > > + > > +maintainers: > > + - Yuntao Dai <d1581209858@xxxxxxxx> > > + > > +description: > > + The Sophgo cv18x SoCs mailbox has 8 channels and 8 bytes per channel for > > + different processors. Any processer can write data in a channel, and > > + set co-responding register to raise interrupt to notice another processor, > > + and it is allowed to send data to itself. > > + Sophgo cv18x SoCs has 3 processors and numbered as > > + <1> C906L > > + <2> C906B > > + <3> 8051 > > + > > +properties: > > + compatible: > > + enum: > > + - sophgo,cv1800b-mailbox > > "sophgo,cv1800-mailbox" please. > I will fix it > > + > > + reg: > > + maxItems: 1 > > -- > > 2.17.1 > > Best regards, Yuntao Dai
