On Tue, Jun 18, 2024 at 10:56:16AM +0100, Suzuki K Poulose wrote: > On 18/06/2024 08:27, Jie Gan wrote: > > Add binding document for Coresight Slave Register device. > > Is this a made up name of the driver ? CoreSight Slave Register > device sounds nowhere near to what it does. If you have a proper > name for the "IP" please use that. We will reconsider the device name. Thanks for your reminding. > > > > > Add a new property to TMC, qcom,csr-atid-offset, to indicate which > > ATID registers will be used by the TMC ETR. Each TMC ETR device is > > associated with four ATID registers that are continuous in address. > > > > Signed-off-by: Jie Gan <quic_jiegan@xxxxxxxxxxx> > > --- > > .../bindings/arm/arm,coresight-tmc.yaml | 8 ++ > > .../bindings/arm/qcom,coresight-csr.yaml | 76 +++++++++++++++++++ > > 2 files changed, 84 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > > index cb8dceaca70e..295641a96c21 100644 > > --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > > +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml > > @@ -82,6 +82,14 @@ properties: > > $ref: /schemas/types.yaml#/definitions/uint32 > > maximum: 15 > > + qcom,csr-atid-offset: > > + description: > > + Offset to the coresight slave register component's ATID register > > + that is used by specific TMC ETR. The ATID register can be programed according > > + to the trace id to filter out specific trace data which gets through the ETR > > + to the downstream components. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Why do we need this ? Could this not be inferred from the "input port" to > which this ETR is connected on the CSR ? > > e.g., input-0 : Offset 0 > input-1 : Offset for Bank1 > We will try this suggestion. Thanks, Jie > > > > > + > > in-ports: > > $ref: /schemas/graph.yaml#/properties/ports > > additionalProperties: false > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml > > new file mode 100644 > > index 000000000000..16f97cbe3d4b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml > > @@ -0,0 +1,76 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: CoreSight Slave Register > > + > > +maintainers: > > + - Yuanfang Zhang <quic_yuanfang@xxxxxxxxxxx> > > + - Mao Jinlong <quic_jinlmao@xxxxxxxxxxx> > > + - Jie Gan <quic_jiegan@xxxxxxxxxxx> > > + > > +description: > > + The Coresight Slave Register controls various Coresight behaviors. > > + Used to enable/disable ETR’s data filter function based on trace ID. > > + > > +properties: > > + compatible: > > + const: qcom,coresight-csr > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + maxItems: 1 > > + items: > > + - const: apb_pclk > > + > > + reg-names: > > + items: > > + - const: csr-base > > + > > + in-ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + patternProperties: > > + '^port(@[0-7])?$': > > + description: Input connections from CoreSight Trace bus > > + $ref: /schemas/graph.yaml#/properties/port > > + > > +required: > > + - compatible > > + - reg > > + - in-ports > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscon@10001000 { > > + compatible = "qcom,coresight-csr"; > > + reg = <0x0 0x10001000 0x0 0x1000>; > > + reg-names = "csr-base"; > > + > > + in-ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + csr_in_port0: endpoint { > > + remote-endpoint = <&etr0_out_port>; > > + }; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + csr_in_port1: endpoint { > > + remote-endpoint = <&etr1_out_port>; > > + }; > > + }; > > + }; > > + }; >
