On Mon, Jun 10, 2024 at 03:48:42PM +0300, Dmitry Rokosov wrote: > On Mon, Jun 10, 2024 at 01:47:06PM +0200, Jerome Brunet wrote: > > On Mon 10 Jun 2024 at 14:18, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> wrote: > > > > > Hello Jerome, > > > > > > Thank you for the review! > > > > > > On Mon, Jun 10, 2024 at 12:04:09PM +0200, Jerome Brunet wrote: > > >> On Wed 15 May 2024 at 21:47, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> wrote: > > >> > > >> > Add the documentation and dt bindings for Amlogic A1 CPU clock > > >> > controller. > > >> > > > >> > This controller consists of the general 'cpu_clk' and two main parents: > > >> > 'cpu fixed clock' and 'syspll'. The 'cpu fixed clock' is an internal > > >> > fixed clock, while the 'syspll' serves as an external input from the A1 > > >> > PLL clock controller. > > >> > > > >> > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > > >> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > >> > --- > > >> > .../bindings/clock/amlogic,a1-cpu-clkc.yaml | 64 +++++++++++++++++++ > > >> > .../dt-bindings/clock/amlogic,a1-cpu-clkc.h | 19 ++++++ > > >> > 2 files changed, 83 insertions(+) > > >> > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml > > >> > create mode 100644 include/dt-bindings/clock/amlogic,a1-cpu-clkc.h > > >> > > > >> > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml > > >> > new file mode 100644 > > >> > index 000000000000..f4958b315ed4 > > >> > --- /dev/null > > >> > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml > > >> > @@ -0,0 +1,64 @@ > > >> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > >> > +%YAML 1.2 > > >> > +--- > > >> > +$id: http://devicetree.org/schemas/clock/amlogic,a1-cpu-clkc.yaml# > > >> > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > >> > + > > >> > +title: Amlogic A1 CPU Clock Control Unit > > >> > + > > >> > +maintainers: > > >> > + - Neil Armstrong <neil.armstrong@xxxxxxxxxx> > > >> > + - Jerome Brunet <jbrunet@xxxxxxxxxxxx> > > >> > + - Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > > >> > + > > >> > +properties: > > >> > + compatible: > > >> > + const: amlogic,a1-cpu-clkc > > >> > + > > >> > + '#clock-cells': > > >> > + const: 1 > > >> > + > > >> > + reg: > > >> > + maxItems: 1 > > >> > + > > >> > + clocks: > > >> > + items: > > >> > + - description: input fixed pll div2 > > >> > + - description: input fixed pll div3 > > >> > + - description: input sys pll > > >> > + - description: input oscillator (usually at 24MHz) > > >> > > >> According to the documentation, fdiv5 is also an input of the CPU clock > > >> tree. > > >> > > >> That is typically the kind of things we'd prefer to get right from the > > >> beginning to avoid modifying the bindings later. > > >> > > > > > > Could you please share which documentation you are referencing? I have > > > the A113L documentation, and there is no mention of the CPU clock IP. > > > > You should get in touch with Amlogic. > > > > Okay, I will double check with Amlogic and back with accurate > information. > According to a statement from an Amlogic FAE, there is an error in the datasheet's CPU clock controller figure. The FAE clarified the following: """ The d5/d7 clock source inside the A1 chip is not supplied to CPU_CLK and is instead used by other peripherals. Therefore, you can connect a fixed frequency divider (div5/div7) to peripherals in A1. The CPU control only supports fclk_div2/div3. """ [...] -- Thank you, Dmitry
