On Tue, 11 Jun 2024, Andrea della Porta wrote: > Hi, > I'm on the verge of reworking the RP1 driver from downstream in order for it to be > in good shape for upstream inclusion. > RP1 is an MFD chipset that acts as a south-bridge PCIe endpoint sporting a pletora > of subdevices (i.e. Ethernet, USB host controller, I2C, PWM, etc.) whose registers > are all reachable starting from an offset from the BAR address. It's less of an MFD and more of an SoC. Please refrain from implemented entire SoCs in drivers/mfd. Take a look in drivers/soc and drivers/platform. -- Lee Jones [李琼斯]
