Re : [PATCH v1] riscv: dts: starfive: add PCIe dts configuration for JH7110

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 




> 
> On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote:
> > Add PCIe dts configuraion for JH7110 SoC platform.
> >
> > Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx>
> > Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> > ---
> >  .../boot/dts/starfive/jh7110-common.dtsi      | 64 ++++++++++++++
> >  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 86 +++++++++++++++++++
> >  2 files changed, 150 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > index 8ff6ea64f048..1da7379f4e08 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > @@ -294,6 +294,22 @@
> >  	status = "okay";
> >  };
> >
> > +&pcie0 {
> > +	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> > +	phys = <&pciephy0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie0_pins>;
> > +	status = "okay";
> > +};
> > +
> > +&pcie1 {
> > +	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> > +	phys = <&pciephy1>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pcie1_pins>;
> > +	status = "okay";
> > +};
> 
> Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I
> assume if one does, all does, since they're basically identical?

Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same.





[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux