On Wed 15 May 2024 at 21:47, Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> wrote: > The CPU clock controller plays a general role in the Amlogic A1 SoC > family by generating CPU clocks. As an APB slave module, it offers the > capability to inherit the CPU clock from two sources: the internal fixed > clock known as 'cpu fixed clock' and the external input provided by the > A1 PLL clock controller, referred to as 'syspll'. > > It is important for the driver to handle the cpu_clk rate switching > effectively by transitioning to the CPU fixed clock to avoid any > potential execution freezes. > Please group your changes, fixes then bindings then driver.
