Re: [PATCH 13/13] arm64: dts: qcom: Add support for multimedia clock controllers

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On 6/2/2024 9:47 AM, Bjorn Andersson wrote:
On Fri, May 31, 2024 at 02:32:49PM GMT, Taniya Das wrote:
Add support for camera, display0, display1 and video clock
controllers on SA8775P platform. While at it, update the
sleep_clk frequency.

Whenever you feel like starting a sentence with "While at it", it's
probably a separate commit - and indeed so in this case. This will also
give you the opportunity to claim why you're changing its value...

I will split the changes to take care in next series.

Regards,
Bjorn


Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
---
  arch/arm64/boot/dts/qcom/sa8775p-ride.dts |  2 +-
  arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 59 +++++++++++++++++++++++
  2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 26ad05bd3b3f..4684da376565 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -542,7 +542,7 @@
  };
&sleep_clk {
-	clock-frequency = <32764>;
+	clock-frequency = <32000>;
  };
&spi16 {
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index eae0de9720b5..7f62738671da 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6,8 +6,11 @@
  #include <dt-bindings/interconnect/qcom,icc.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
  #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
  #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
  #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
  #include <dt-bindings/mailbox/qcom-ipcc.h>
  #include <dt-bindings/power/qcom-rpmpd.h>
@@ -2904,6 +2907,47 @@
  			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
  		};
+ videocc: clock-controller@abf0000 {
+			compatible = "qcom,sa8775p-videocc";
+			reg = <0x0 0x0abf0000 0x0 0x10000>;
+			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ade0000 {
+			compatible = "qcom,sa8775p-camcc";
+			reg = <0x0 0x0ade0000 0x0 0x20000>;
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc0: clock-controller@af00000 {
+			compatible = "qcom,sa8775p-dispcc0";
+			reg = <0x0 0x0af00000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
  		pdc: interrupt-controller@b220000 {
  			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
  			reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -3424,6 +3468,21 @@
  			#freq-domain-cells = <1>;
  		};
+ dispcc1: clock-controller@22100000 {
+			compatible = "qcom,sa8775p-dispcc1";
+			reg = <0x0 0x22100000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
  		ethernet1: ethernet@23000000 {
  			compatible = "qcom,sa8775p-ethqos";
  			reg = <0x0 0x23000000 0x0 0x10000>,
--
2.17.1


--
Thanks & Regards,
Taniya Das.




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