On 30.05.2024 20:38, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Enable parsing of variable configuration for all architectures. This patch
> is in preparation for adding support for the RZ/V2H SoC, which utilizes the
> ARM64 architecture and features port pins with variable configuration.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> # on RZ/G3S
> ---
> v2->v3
> - Included RB tag
>
> RFC->v2
> - No change
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 84d5882099a0..89716e842c63 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -317,7 +317,6 @@ struct rzg2l_pinctrl {
>
> static const u16 available_ps[] = { 1800, 2500, 3300 };
>
> -#ifdef CONFIG_RISCV
> static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
> u64 pincfg,
> unsigned int port,
> @@ -336,6 +335,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
> return 0;
> }
>
> +#ifdef CONFIG_RISCV
> static const u64 r9a07g043f_variable_pin_cfg[] = {
> RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
> PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
> @@ -2219,13 +2219,11 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
> if (i && !(i % RZG2L_PINS_PER_PORT))
> j++;
> pin_data[i] = pctrl->data->port_pin_configs[j];
> -#ifdef CONFIG_RISCV
> if (pin_data[i] & PIN_CFG_VARIABLE)
> pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
> pin_data[i],
> j,
> i % RZG2L_PINS_PER_PORT);
> -#endif
> pins[i].drv_data = &pin_data[i];
> }
>
