--- Current WIP ported from downstream kernel. Still a lot of TODOs and missing parts. It's the same approach as imx8-ss-lsio.dtsi and friends which are supposed to be included inside the DT root node, not at the end. .../boot/dts/freescale/imx8-ss-lvds0.dtsi | 574 ++++++++++++++++++ 1 file changed, 574 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi new file mode 100644 index 0000000000000..8ad13962925d0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +mipi_ipg_clk: clock-mipi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_ipg_clk"; +}; + +mipi_pll_div2_clk: clock-mipi-div2-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + clock-output-names = "mipi_pll_div2_clk"; +}; + +lvds_subsys: bus@56200000 { + compatible = "simple-bus"; + reg = <0x56200000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + lvds0_subsys: bus@56220000 { + compatible = "simple-bus"; + reg = <0x56220000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&irqsteer_mipi_lvds0>; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds0_csr: syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + status = "disabled"; + + mipi_lvds0_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = <IMX_SC_R_MIPI_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + // mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + // reg = <1>; + // remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + // }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + // mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + // reg = <1>; + // remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + // }; + }; + }; + }; + + mipi_lvds_0_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + // channel@1 { + // #address-cells = <1>; + // #size-cells = <0>; + // reg = <1>; + // phys = <&mipi_lvds_0_phy>; + // phy-names = "lvds_phy"; + + // port@0 { + // reg = <0>; + + // mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + // remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + // }; + // }; + + // port@1 { + // reg = <1>; + + // /* ... */ + // }; + // }; + }; + }; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds0_di_mipi_lvds_regs_lpcg: clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "mipi_lvds0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4 IMX_LPCG_CLK_1>; + clock-output-names = "mipi0_pwm_lpcg_clk", + "mipi0_pwm_lpcg_ipg_clk", + "mipi0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>; + clock-output-names = "mipi0_i2c0_lpcg_clk", + "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi0_i2c1_lpcg: clock-controller@56223014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>; + clock-output-names = "mipi0_i2c1_lpcg_clk", + "mipi0_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + clocks = <&mipi0_pwm_lpcg 0>, + <&mipi0_pwm_lpcg 1>, + <&mipi0_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupts = <8>; + clocks = <&mipi0_i2c0_lpcg 0>, + <&mipi0_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_0_phy: phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + /* TODO MIPI DSI0 */ + }; + + // mipi0_dsi_host: dsi_host@56228000 { + // #address-cells = <1>; + // #size-cells = <0>; + // compatible = "fsl,imx8qx-nwl-dsi"; + // reg = <0x56228000 0x300>; + // clocks = <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PER>, + // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_BYPASS>, + // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_PHY>, + // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_MST_BUS>, + // <&clk IMX_SC_R_MIPI_0 IMX_SC_PM_CLK_SLV_BUS>, + // <&mipi_pll_div2_clk>; + // clock-names = "pixel", + // "bypass", + // "phy_ref", + // "tx_esc", + // "rx_esc", + // "phy_parent"; + // interrupts = <16>; + // power-domains = <&pd IMX_SC_R_MIPI_0>; + // phys = <&mipi0_dphy>; + // phy-names = "dphy"; + // csr = <&lvds_region1>; + // use-disp-ss; + // status = "disabled"; + + // ports { + // #address-cells = <1>; + // #size-cells = <0>; + + // mipi0_in: port@0 { + // #address-cells = <1>; + // #size-cells = <0>; + + // reg = <0>; + // mipi0_dsi_in: endpoint@0 { + // reg = <0>; + // remote-endpoint = <&dpu_disp0_mipi_dsi>; + // }; + // }; + // }; + // }; + + lvds1_subsys: bus@56240000 { + compatible = "simple-bus"; + reg = <0x56240000 0x30000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&irqsteer_mipi_lvds1>; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds1_csr: syscon@56241000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56241000 0x1000>; + clocks = <&mipi_lvds1_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + status = "disabled"; + + mipi_lvds1_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = <IMX_SC_R_MIPI_1>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_1_pxl2dpi>; + }; + + // mipi_lvds_1_pxl2dpi_dc0_pixel_link1: endpoint@1 { + // reg = <1>; + // remote-endpoint = <&dc0_pixel_link1_mipi_lvds_1_pxl2dpi>; + // }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi>; + }; + + // mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1: endpoint@1 { + // reg = <1>; + // remote-endpoint = <&mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi>; + // }; + }; + }; + }; + + mipi_lvds_1_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_1_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + // channel@1 { + // #address-cells = <1>; + // #size-cells = <0>; + // reg = <1>; + // phys = <&mipi_lvds_1_phy>; + // phy-names = "lvds_phy"; + + // port@0 { + // reg = <0>; + + // mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi: endpoint { + // remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1>; + // }; + // }; + + // port@1 { + // reg = <1>; + + // /* ... */ + // }; + // }; + }; + }; + + mipi1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds1_di_mipi_lvds_regs_lpcg: clock-controller@56243004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_4>; + clock-output-names = "mipi_lvds1_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4 IMX_LPCG_CLK_1>; + clock-output-names = "mipi1_pwm_lpcg_clk", + "mipi1_pwm_lpcg_ipg_clk", + "mipi1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>; + clock-output-names = "mipi1_i2c0_lpcg_clk", + "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi1_i2c1_lpcg: clock-controller@56243014 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243014 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0 IMX_LPCG_CLK_4>; + clock-output-names = "mipi1_i2c1_lpcg_clk", + "mipi1_i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + clocks = <&mipi1_pwm_lpcg 0>, + <&mipi1_pwm_lpcg 1>, + <&mipi1_pwm_lpcg 2>; + clock-names = "per", "ipg", "32k"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupts = <8>; + clocks = <&mipi1_i2c0_lpcg 0>, + <&mipi1_i2c0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_1_phy: phy@56248300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds1_csr>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + /* TODO MIPI DSI1 */ + }; + + // mipi1_dsi_host: dsi_host@56248000 { + // #address-cells = <1>; + // #size-cells = <0>; + // compatible = "fsl,imx8qx-nwl-dsi"; + // reg = <0x56248000 0x300>; + // clocks = <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PER>, + // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_BYPASS>, + // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_PHY>, + // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_MST_BUS>, + // <&clk IMX_SC_R_MIPI_1 IMX_SC_PM_CLK_SLV_BUS>, + // <&mipi_pll_div2_clk>; + // clock-names = "pixel", + // "bypass", + // "phy_ref", + // "tx_esc", + // "rx_esc", + // "phy_parent"; + // interrupts = <16>; + // power-domains = <&pd IMX_SC_R_MIPI_1>; + // phys = <&mipi1_dphy>; + // phy-names = "dphy"; + // csr = <&lvds_region2>; + // use-disp-ss; + // status = "disabled"; + + // ports { + // #address-cells = <1>; + // #size-cells = <0>; + + // mipi1_in: port@0 { + // #address-cells = <1>; + // #size-cells = <0>; + + // reg = <0>; + // mipi1_dsi_in: endpoint@0 { + // reg = <0>; + // remote-endpoint = <&dpu_disp1_mipi_dsi>; + // }; + // }; + // }; + // }; + +}; -- 2.34.1