Hello Trevor, On Wed, Jun 05, 2024 at 04:35:04PM -0400, Trevor Gamblin wrote: > Resending due to missing real name in "From:" line. > > This series adds support for the AXI PWM GEN subsystem found on FPGA IP > cores. It can be used to generate configurable PWM outputs, and includes > options for external synchronization and clock signals. The work is > being done on behalf of, and therefore lists maintainers from Analog > Devices, Inc. > > The series has been tested on actual hardware using an EVAL-AD7985FMCZ > evaluation board. An oscilloscope was used to validate that the > generated PWM signal matched the requested one. > > There was previously a follow-up series > (https://lore.kernel.org/linux-pwm/20240314204722.1291993-1-tgamblin@xxxxxxxxxxxx/) > that enabled support for two different versions of the AXI PWM GEN IP. > Since issues were identified with the v1 IP functionality and v2's > regmap is the one listed on the device wiki > (https://analogdevicesinc.github.io/hdl/library/axi_pwm_gen/index.html), > the driver was changed to support only the v2 IP after squashing those > additions. As a result, the overall driver is simpler as it no longer > uses an axi_pwm_variant struct. Support for v1 IP can be added back > later in the event that it is required. I found a minor nitpick in your patch. I applied it anyhow and jumped at the patch opportunity myself. Patch in your inbox (or at https://lore.kernel.org/linux-pwm/20240606164047.534741-6-u.kleine-koenig@xxxxxxxxxxxx) Best regards and thanks for your contribution! Uwe
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