On 05/06/2024 09:51, Alisa-Dariana Roman wrote:
> There are actually 4 configuration modes of clock source for AD719X
> devices. Either a crystal can be attached externally between MCLK1 and
> MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
> pin. The other 2 modes make use of the 4.92MHz internal clock, which can
> be made available on the MCLK2 pin.
>
> The presence of an external clock is optional, not required.
Why?
>
> Fixes: f7356e47032c ("dt-bindings: iio: adc: ad7192: Add binding documentation for AD7192")
> Signed-off-by: Alisa-Dariana Roman <alisa.roman@xxxxxxxxxx>
> ---
> .../bindings/iio/adc/adi,ad7192.yaml | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> index a03da9489ed9..c5a4219a9388 100644
> --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
> @@ -39,11 +39,16 @@ properties:
>
> clocks:
> maxItems: 1
> - description: phandle to the master clock (mclk)
> + description: |
> + Optionally, either a crystal can be attached externally between MCLK1 and
> + MCLK2 pins, or an external CMOS-compatible clock can drive the MCLK2
> + pin. If absent, internal 4.92MHz clock is used which can be made available
> + on MCLK2.
>
> clock-names:
> - items:
> - - const: mclk
> + enum:
> + - xtal
> + - clk
This mclk->clk breaks the users.
Best regards,
Krzysztof
