On Tue, Jun 04, 2024 at 07:05:12PM +0300, Abel Vesa wrote:
> All PCIe controllers found on X1E80100 have MHI register region and
> VDDPE supplies. Add them to the schema as well.
>
> Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller")
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> ---
> This patchset fixes the following warning:
> https://lore.kernel.org/all/171751454535.785265.18156799252281879515.robh@xxxxxxxxxx/
>
> Also fixes a MHI reg region warning that will be triggered by the following patch:
> https://lore.kernel.org/all/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@xxxxxxxxxx/
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> index 1074310a8e7a..7ceba32c4cf9 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
> @@ -19,11 +19,10 @@ properties:
> const: qcom,pcie-x1e80100
>
> reg:
> - minItems: 5
> + minItems: 6
> maxItems: 6
>
> reg-names:
> - minItems: 5
> items:
> - const: parf # Qualcomm specific registers
> - const: dbi # DesignWare PCIe registers
> @@ -71,6 +70,9 @@ properties:
> - const: pci # PCIe core reset
> - const: link_down # PCIe link down reset
>
> + vddpe-3v3-supply:
> + description: A phandle to the PCIe endpoint power supply
TBC, this is a rail on the host side provided to a card? If so, we have
standard properties for standard PCI voltage rails. It is also preferred
that you put them in a root port node rather than the host bridge.
Rob
