Add mule NVRAM and ROM on the Mule I2C mux (0x18).
Signed-off-by: Farouk Bouabid <farouk.bouabid@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 45 +++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
index eea906379983..62591972df02 100644
--- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
@@ -10,6 +10,8 @@
/ {
aliases {
i2c10 = &i2c10;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
mmc0 = &emmc;
mmc1 = &sdio;
rtc0 = &rtc_twi;
@@ -309,6 +311,49 @@ fan: fan@18 {
#cooling-cells = <2>;
};
};
+
+ i2c12: i2c@2 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@18 {
+ compatible = "atmel,24c02";
+ reg = <0x18>;
+ size = <8>;
+ };
+ };
+
+ i2c13: i2c@3 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@18 {
+ compatible = "atmel,24c02";
+ reg = <0x18>;
+ read-only;
+ size = <32>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mule-variant@0 {
+ reg = <0x0 0x1>;
+ };
+
+ mule-bl-version@1 {
+ reg = <0x1 0x8>;
+ };
+
+ mule-version@9 {
+ reg = <0x9 0x8>;
+ };
+ };
+ };
+ };
};
rtc_twi: rtc@6f {
--
2.34.1
