On Wed, May 29, 2024 at 08:07:14AM +0200, Amna Waseem wrote: > Add a property to the binding to configure the Alert Polarity. > Alert pin is asserted based on the value of Alert Polarity bit of > Mask/Enable register. It is by default 0 which means Alert pin is > configured to be active low. To configure it to active high, set > alert-polarity property value to 1. > > Signed-off-by: Amna Waseem <Amna.Waseem@xxxxxxxx> > --- > Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml > index df86c2c92037..a3f0fd71fcc6 100644 > --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml > +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml > @@ -66,6 +66,14 @@ properties: > description: phandle to the regulator that provides the VS supply typically > in range from 2.7 V to 5.5 V. > > + alert-polarity: > + description: | > + Alert polarity bit value of Mask/Enable register. Alert pin is asserted > + based on the value of Alert polarity Bit. Default value is active low. > + 0 selects active low, 1 selects active high. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1] This is alert as in SMBus Alert? That's handled as an interrupt, but this binding has no interrupt property. And the interrupt binding provides a way already to specify active trigger state. Why do we need a second way to do this? Rob
