On 5/15/24 13:12, Beniamin Sandu wrote:
This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Beniamin Sandu <beniaminsandu@xxxxxxxxx>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index cbbc53c47921..0def0b0daaf7 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x0>;
};
@@ -41,6 +42,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x1>;
};
@@ -48,6 +50,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x2>;
};
@@ -55,8 +58,15 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&l2_shared>;
reg = <0x3>;
};
+
+ l2_shared: cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
};
firmware {
Applied!
Thanks,
Dinh
