This patch adds new options to select a clock source and DIV_M register
value for each coupled PWM channels.
Signed-off-by: Hironori KIKUCHI <kikuchan98@xxxxxxxxx>
---
.../bindings/pwm/allwinner,sun20i-pwm.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
index b9b6d7e7c87..436a1d344ab 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
@@ -45,6 +45,25 @@ properties:
description: The number of PWM channels configured for this instance
enum: [6, 9]
+ allwinner,pwm-pair-clock-sources:
+ description: The clock source names for each PWM pair
+ items:
+ enum: [hosc, apb]
+ minItems: 1
+ maxItems: 8
+
+ allwinner,pwm-pair-clock-prescales:
+ description: The prescale (DIV_M register) values for each PWM pair
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ minimum: 0
+ maximum: 8
+ minItems: 1
+ maxItems: 1
+ minItems: 1
+ maxItems: 8
+
allOf:
- $ref: pwm.yaml#
--
2.45.1
