On 5/30/24 01:18, Amna Waseem wrote:
On 5/29/24 16:01, Guenter Roeck wrote:
On 5/29/24 00:07, Krzysztof Kozlowski wrote:
On 29/05/2024 08:07, Amna Waseem wrote:
Add a property to the binding to configure the Alert Polarity.
Alert pin is asserted based on the value of Alert Polarity bit of
Mask/Enable register. It is by default 0 which means Alert pin is
configured to be active low. To configure it to active high, set
alert-polarity property value to 1.
Signed-off-by: Amna Waseem <Amna.Waseem@xxxxxxxx>
---
Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
index df86c2c92037..a3f0fd71fcc6 100644
--- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
+++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml
@@ -66,6 +66,14 @@ properties:
description: phandle to the regulator that provides the VS supply typically
in range from 2.7 V to 5.5 V.
+ alert-polarity:
Missing vendor prefix.
Are you sure you want a vendor prefix here ? Reason for asking is that
many hardware monitoring chips have configurable alert or interrupt polarity,
only the name is different. Some examples are the JC42.4 standard ("event
polarity"), adt7410/adt7420 "interrupt polarity", MAX31827 ("alarm polarity"),
or DS1621 ("output polarity"). We even have a vendor property, "adi,alarm-pol",
used for MAX31827.
Secondary problem is that not all chips of the series support this
configuration. INA209 has a configurable "warning polarity", but the
warning pin and the smbus alert pin are two different pins.
INA219 and INA220 do not have alert or interrupt output pins.
Only INA226, INA230, INA231, INA238, and INA260 support configurable
alert polarity.
Thanks,
Guenter
I agree with not using vendor prefix with alert-polarity property. @Krzysztof Kozlowski what do you suggest?
The version with vendor prefix was already accepted, so let's just go with it.
It is not worth arguing. We can revisit if there is ever the need to support
this for other chips.
Thanks,
Guenter
