On 27/05/2024 11:37, Conor Dooley wrote:
> The PCI host controller on PolarFire SoC has multiple "instances", each
> with their own bridge and ctrl address spaces. The original binding has
> an "apb" register region, and it is expected to be set to the base
> address of the host controllers register space. Some defines in the
> Linux driver were used to compute the addresses of the bridge and ctrl
> address ranges corresponding to instance1. Some customers want to use
> instance2 however and that requires changing the defines in the driver,
> which is clearly not a portable solution.
>
> Remove this "apb" register region from the binding and add "bridge" &
> "ctrl" regions instead, that will directly communicate the address of
> these regions
>
> Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
> .../devicetree/bindings/pci/microchip,pcie-host.yaml | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Best regards,
Krzysztof
