Re: [EXT] Re: [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock Enclave

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On Fri, May 24, 2024 at 12:08:14PM +0000, Pankaj Gupta wrote:
> 
> 
> > -----Original Message-----
> > From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> > Sent: Friday, May 24, 2024 4:04 PM
> > To: Pankaj Gupta <pankaj.gupta@xxxxxxx>
> > Cc: Jonathan Corbet <corbet@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>;
> > Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>; Conor Dooley
> > <conor+dt@xxxxxxxxxx>; Shawn Guo <shawnguo@xxxxxxxxxx>; Pengutronix
> > Kernel Team <kernel@xxxxxxxxxxxxxx>; Fabio Estevam
> > <festevam@xxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof Kozlowski
> > <krzk+dt@xxxxxxxxxx>; linux-doc@xxxxxxxxxxxxxxx; linux-
> > kernel@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx;
> > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> > Subject: [EXT] Re: [PATCH v2 4/5] firmware: imx: add driver for NXP EdgeLock
> > Enclave
> >
> > Caution: This is an external email. Please take care when clicking links or
> > opening attachments. When in doubt, report the message using the 'Report
> > this email' button
> >
> >
> > On Thu, May 23, 2024 at 04:19:35PM +0530, Pankaj Gupta wrote:
> > > NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE), are
> > > embedded in the SoC to support the features like HSM, SHE & V2X, using
> > > message based communication interface.
> > >
> > > The secure enclave FW communicates on a dedicated messaging unit(MU)
> > > based interface(s) with application core, where kernel is running.
> > > It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
> > >
> > > This patch adds the driver for communication interface to
> > > secure-enclave, for exchanging messages with NXP secure enclave HW
> > > IP(s) like EdgeLock Enclave (ELE) from Kernel-space, used by kernel
> > > management layers like
> > > - DM-Crypt.
> > >
> > > Signed-off-by: Pankaj Gupta <pankaj.gupta@xxxxxxx>
> > > ---
> > >  drivers/firmware/imx/Kconfig        |  12 +
> > >  drivers/firmware/imx/Makefile       |   2 +
> > >  drivers/firmware/imx/ele_base_msg.c | 286 +++++++++++++++++++
> > > drivers/firmware/imx/ele_base_msg.h |  92 +++++++
> > >  drivers/firmware/imx/ele_common.c   | 239 ++++++++++++++++
> > >  drivers/firmware/imx/ele_common.h   |  43 +++
> > >  drivers/firmware/imx/se_ctrl.c      | 531
> > ++++++++++++++++++++++++++++++++++++
> > >  drivers/firmware/imx/se_ctrl.h      |  99 +++++++
> > >  include/linux/firmware/imx/se_api.h |  14 +
> > >  9 files changed, 1318 insertions(+)
> > >
> >
> > > +static int se_probe_if_cleanup(struct platform_device *pdev) {
> > > +     struct device *dev = &pdev->dev;
> > > +     struct se_if_priv *priv;
> > > +     int ret = 0;
> > > +
> > > +     priv = dev_get_drvdata(dev);
> > > +     if (!priv) {
> > > +             ret = 0;
> > > +             dev_dbg(dev, "SE-MU Priv data is NULL;");
> > > +             return ret;
> > > +     }
> > > +
> > > +     if (priv->tx_chan)
> > > +             mbox_free_channel(priv->tx_chan);
> > > +     if (priv->rx_chan)
> > > +             mbox_free_channel(priv->rx_chan);
> > > +
> > > +     /* free the buffer in se remove, previously allocated
> > > +      * in se probe to store encrypted IMEM
> > > +      */
> > > +     if (priv->imem.buf) {
> > > +             dmam_free_coherent(dev,
> > > +                                ELE_IMEM_SIZE,
> > > +                                priv->imem.buf,
> > > +                                priv->imem.phyaddr);
> > > +             priv->imem.buf = NULL;
> > > +     }
> > > +
> > > +     if (priv->flags & RESERVED_DMA_POOL) {
> > > +             of_reserved_mem_device_release(dev);
> >
> > You can call this unconditionally, no need to keep track if you called
> > of_reserved_mem_device_init() successfully.
> 
> But it will not be called for each SoC.
> The memory is not reserved for i.MX95 platforms.
> This is required.

Again: You can call this unconditionally. Look at the code,
of_reserved_mem_device_release() won't do anything if you haven't called
of_reserved_mem_device_init() before.

Sascha

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