On Tue, May 21, 2024 at 10:09:09PM +0200, Francesco Dolcini wrote: > On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote: > > TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely > > PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of > > these PCIe instances. > > What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to > add all 3, not just the first twos. Thank you for reviewing the patch. I agree that it was incorrect for me to mention that J784S4 has two instances of PCIe. It actually has 4 instances as mentioned in the Excel Sheet provided along with the Technical Reference Manual at: https://www.ti.com/lit/zip/spruj52 namely PCIe0, PCIe1, PCIe2 and PCIe3. Since the J784S4 EVM has only PCIe0 and PCIe1 instances of PCIe brought out, I was able to test them and therefore added support for only those two instances in this series. However I do agree that all 4 should be added to the SoC file (k3-j784s4-main.dtsi) for the sake of completeness in terms of describing the SoC, while the Board file (k3-j784s4-evm.dts) can still contain just PCIe0 and PCIe1 as those are the ones brought out on the board. I will implement your suggestion in the v3 series. Regards, Siddharth.
