On Tue, Feb 24, 2015 at 8:58 AM, Michal Simek <michal.simek@xxxxxxxxxx> wrote:
> On 02/24/2015 03:42 PM, Rob Herring wrote:
>> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@xxxxxxxxxx> wrote:
>>> Initial version of device tree for Xilinx ZynqMP SoC.
>>>
>>> Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
>>> Acked-by: Sören Brinkmann <soren.brinkmann@xxxxxxxxxx>
>>> ---
>>
>> [...]
>>
>>> + gic: interrupt-controller@f9010000 {
>>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>>
>> gic-400, right?
>
> yep
>
>>
>>> + #interrupt-cells = <3>;
>>> + reg = <0x0 0xf9010000 0x10000>,
>>> + <0x0 0xf9020000 0x20000>,
>>> + <0x0 0xf9040000 0x20000>,
>>> + <0x0 0xf9060000 0x20000>;
>>
>> These addresses are wrong if you are doing address swizzling to do 64K
>> offsets. We don't really have an answer yet as to what is the right
>> way. See the XGene GIC discussion[1].
>
> Is this better for GICC?
> <0x0 0xf902f000 0x2000>
Yes, and the VCPU interface needs this as well. As far as sizes, we're
still discussing that.
Rob
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