The i.MX8MM Menlo carrier board uses dedicated 20 MHz Xtal to supply
clock to second SPI CAN controller on the carrier board as well as
CPLD on the same board. Fix incorrect reuse of SoM 20 MHz Xtal for
that purpose, describe the separate Xtal and use it.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
Cc: Fabio Estevam <festevam@xxxxxxxxx>
Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
Cc: Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Cc: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: imx@xxxxxxxxxxxxxxx
Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
---
arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
index 0b123a84018b2..4c38979f7333f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts
@@ -14,6 +14,13 @@ / {
"toradex,verdin-imx8mm",
"fsl,imx8mm";
+ /* Carrier board Xtal for SPI CAN controller and CPLD */
+ clk20mcb: clk-20m-cb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
/delete-node/ gpio-keys;
leds {
@@ -60,7 +67,7 @@ &ecspi1 {
/* CAN controller on the baseboard */
canfd: can@0 {
compatible = "microchip,mcp2518fd";
- clocks = <&clk_xtal20>;
+ clocks = <&clk20mcb>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
reg = <0>;
--
2.43.0
