On Wed, 15 May 2024 21:47:27 +0300, Dmitry Rokosov wrote: > The 'sys_pll' input is an optional clock that can be used to generate > 'sys_pll_div16', which serves as one of the sources for the GEN clock. > > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > --- > .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 9 +++++++-- > include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h | 1 + > 2 files changed, 8 insertions(+), 2 deletions(-) > Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
