On Wed, 15 May 2024 21:47:25 +0300, Dmitry Rokosov wrote: > The 'syspll' PLL is a general-purpose PLL designed specifically for the > CPU clock. It is capable of producing output frequencies within the > range of 768MHz to 1536MHz. > > The 'syspll_in' source clock is an optional parent connection from the > peripherals clock controller. > > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> > --- > .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 9 +++++++-- > include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 + > 2 files changed, 8 insertions(+), 2 deletions(-) > Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
