This patch adds support for OPP to vote for the performance state of RPMH power domain based upon PCIe speed it got enumerated. QCOM Resource Power Manager-hardened (RPMh) is a hardware block which maintains hardware state of a regulator by performing max aggregation of the requests made by all of the processors. PCIe controller can operate on different RPMh performance state of power domain based up on the speed of the link. And this performance state varies from target to target. It is manadate to scale the performance state based up on the PCIe speed link operates so that SoC can run under optimum power conditions. Add Operating Performance Points(OPP) support to vote for RPMh state based upon GEN speed link is operating. Before link up PCIe driver will vote for the maximum performance state. As now we are adding ICC BW vote in OPP, the ICC BW voting depends both GEN speed and link width using opp-level to indicate the opp entry table will be difficult. In PCIe certain gen speeds like 2.5GT/s x2 & 5.0 GT/s X1 or 8.0 GT/s x2 & 16GT/s x1 use same ICC bw if we use freq in the OPP table to represent the PCIe speed number of PCIe entries can reduced. So going back to use freq in the OPP table instead of level. To access PCIe registers of the host controller and endpoint PCIe BAR space, config space the CPU-PCIe ICC (interconnect) path should be voted otherwise it may lead to NoC (Network on chip) timeout. We are surviving because of other driver voting for this path. As there is less access on this path compared to PCIe to mem path add minimum vote i.e 1KBps bandwidth always which is sufficient enough to keep the path active and is recommended by HW team. In suspend to ram case there can be some DBI access. Except in suspend to ram case disable CPU-PCIe ICC path after register space access is done. Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> --- Changes from v12: - removed icc bw of the memory path as suggested by mayank - Added check for icc_set_bw in the suspend path as suggested by mani. - Link to v12: https://lore.kernel.org/r/20240427-opp_support-v12-0-f6beb0a1f2fc@xxxxxxxxxxx Changes from v11: - added nicpicks suggested by mani. - Link to v11: https://lore.kernel.org/r/20240423-opp_support-v11-0-15fdd40b0f95@xxxxxxxxxxx Changes from v10: - Updated comments and logs as suggested by mani. - Link to v10: https://lore.kernel.org/r/20240409-opp_support-v10-0-1956e6be343f@xxxxxxxxxxx Changes from v9: - Disable interconnect CPU-PCIe path only system is not suspend to ram case. - If opp find freq fails in the probe fail the probe as suggested by mani. - Modify comments as suggested by mani - Link to v9: https://lore.kernel.org/r/20240407-opp_support-v9-0-496184dc45d7@xxxxxxxxxxx Changes from v8: - Removed the ack-by and reviewed by on dt-bindings as dt-bindings moved to new files. - Removed dt-binding patch for interconnects as it is added in the common file. - Added tags for interconnect as suggested by konrad - Added the comments as suggested by mani - In ICC BW vote for CPU to PCIe path if icc_disable() fails log error and return instead of re-init. - Link to v8: https://lore.kernel.org/linux-arm-msm/20240302-opp_support-v8-0-158285b86b10@xxxxxxxxxxx/ Changes from v7: - Fix the compilation issue in patch3 - Change the commit text and wrap the comments to 80 columns as suggested by bjorn - remove PCIE_MBS2FREQ macro as this is being used by only qcom drivers. - Link to v7: https://lore.kernel.org/r/20240223-opp_support-v7-0-10b4363d7e71@xxxxxxxxxxx Changes from v6: - change CPU-PCIe bandwidth to 1KBps as suggested by HW team. - Create a new API to get frequency based upon PCIe speed as suggested by mani. - Updated few commit texts and comments. - Setting opp to NULL in suspend to remove any votes. - Link for v6: https://lore.kernel.org/linux-arm-msm/20240112-opp_support-v6-0-77bbf7d0cc37@xxxxxxxxxxx/ Changes from v5: - Add ICC BW voting as part of OPP, rebase the latest kernel, and only - either OPP or ICC BW voting will supported we removed the patch to - return error for icc opp update patch. - As we added the icc bw voting in opp table I am not including reviewed - by tags given in previous patch. - Use opp freq to find opp entries as now we need to include pcie link - also in to considerations. - Add CPU-PCIe BW voting which is not present till now. - Drop PCI: qcom: Return error from 'qcom_pcie_icc_update' as either opp or icc bw - only one executes and there is no need to fail if opp or icc update fails. - Link for v5: https://lore.kernel.org/linux-arm-msm/20231101063323.GH2897@thinkpad/T/ Changes from v4: - Added a separate patch for returning error from the qcom_pcie_upadate and moved opp update logic to icc_update and used a bool variable to update the opp. - Addressed comments made by pavan. changes from v3: - Removing the opp vote on suspend when the link is not up and link is not up and add debug prints as suggested by pavan. - Added dev_pm_opp_find_level_floor API to find the highest opp to vote. changes from v2: - Instead of using the freq based opp search use level based as suggested by Dmitry Baryshkov. Changes from v1: - Addressed comments from Krzysztof Kozlowski. - Added the rpmhpd_opp_xxx phandle as suggested by pavan. - Added dev_pm_opp_set_opp API call which was missed on previous patch. --- --- Krishna chaitanya chundru (6): arm64: dts: qcom: sm8450: Add interconnect path to PCIe node PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path dt-bindings: pci: qcom: Add OPP table arm64: dts: qcom: sm8450: Add OPP table support to PCIe PCI: Bring the PCIe speed to MBps logic to new pcie_link_speed_to_mbps() PCI: qcom: Add OPP support to scale performance .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 89 ++++++++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 134 ++++++++++++++++++--- drivers/pci/pci.c | 19 +-- drivers/pci/pci.h | 22 ++++ 5 files changed, 230 insertions(+), 38 deletions(-) --- base-commit: 6c6e47d69d821047097909288b6d7f1aafb3b9b1 change-id: 20240406-opp_support-ca095eb032b4 Best regards, -- Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
