Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Thursday, May 16, 2024 9:52 PM
>
> On Tue, May 14, 2024 at 11:27:30AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Saturday, May 11, 2024 5:03 PM
> > >
> > > On Mon, Apr 15, 2024 at 05:11:34PM +0900, Yoshihiro Shimoda wrote:
> > > > This driver previously supported r8a779f0 (R-Car S4-8). Add support
> > > > for r8a779g0 (R-Car V4H). PCIe features of both r8a779f0 and r8a779g0
> > > > are almost all the same. For example:
> > > > - PCI Express Base Specification Revision 4.0
> > > > - Root complex mode and endpoint mode are supported
> > > >
> > > > However, r8a779g0 requires specific firmware downloading, to
> > > > initialize the PHY. Otherwise, the PCIe controller cannot work.
> > > > The firmware is attached in the manual of the r8a779g0 as text.
> > > > So, convert it to a binary file by using a script.
> > >
> > > The firmware is expected to be present in userspace. So where is it btw? Is it
> > > upstreamed to linux-firmware?
> >
> > I may misunderstand your question, but the firmware is in the SoC's datasheet as
> > a text file. So, we need to convert it to a binary file and store it into the rootfs.
> > (Also, for debug purpose, we can use built-in firmware from "CONFIG_EXTRA_FIRMWARE".)
> >
>
> So how does the conversion need to happen? Does it require any tool or just copy
> the content to a file and pass it as a firmware?
I'm sorry for lack explanation. The way is:
1) copy a text file to a PC.
2) do a script with the text file, and then generate a binary file.
3) copy the binary file to the rootfs of the R-Car.
> Whatever the method is, it should be documented in the commit message (also in
> the driver).
I got it. I'll add such description in the commit and the driver.
> > > You cannot ask users to manually copy the text and convert it to a binary file.
> > > But if the firmware or sequence is not going to change, why can't you hardcode
> > > it in the driver itself?
> >
> > This is because that Renesas is not able to distribute the firmware freely.
> >
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 201 +++++++++++++++++++-
> > > > 1 file changed, 200 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > index 980a916933d6..4e934e9156f2 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > @@ -5,8 +5,10 @@
> > > > */
> > > >
> > > > #include <linux/delay.h>
> > > > +#include <linux/firmware.h>
> > > > #include <linux/interrupt.h>
> > > > #include <linux/io.h>
> > > > +#include <linux/iopoll.h>
> > > > #include <linux/module.h>
> > > > #include <linux/of.h>
> > > > #include <linux/pci.h>
> > > > @@ -20,9 +22,10 @@
> > > > /* Renesas-specific */
> > > > /* PCIe Mode Setting Register 0 */
> > > > #define PCIEMSR0 0x0000
> > > > -#define BIFUR_MOD_SET_ON BIT(0)
> > > > +#define APP_SRIS_MODE BIT(6)
> > > > #define DEVICE_TYPE_EP 0
> > > > #define DEVICE_TYPE_RC BIT(4)
> > > > +#define BIFUR_MOD_SET_ON BIT(0)
> > > >
> > > > /* PCIe Interrupt Status 0 */
> > > > #define PCIEINTSTS0 0x0084
> > > > @@ -37,19 +40,47 @@
> > > > #define PCIEDMAINTSTSEN 0x0314
> > > > #define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> > > >
> > > > +/* Port Logic Registers 89 */
> > > > +#define PRTLGC89 0x0b70
> > > > +
> > > > +/* Port Logic Registers 90 */
> > > > +#define PRTLGC90 0x0b74
> > > > +
> > > > /* PCIe Reset Control Register 1 */
> > > > #define PCIERSTCTRL1 0x0014
> > > > #define APP_HOLD_PHY_RST BIT(16)
> > > > #define APP_LTSSM_ENABLE BIT(0)
> > > >
> > > > +/* PCIe Power Management Control */
> > > > +#define PCIEPWRMNGCTRL 0x0070
> > > > +#define APP_CLK_REQ_N BIT(11)
> > > > +#define APP_CLK_PM_EN BIT(10)
> > > > +
> > > > +/*
> > > > + * The R-Car Gen4 documents don't describe the PHY registers' name.
> > > > + * But, the initialization procedure describes these offsets. So,
> > > > + * this driver makes up own #defines for the offsets.
> > > > + */
> > > > +#define RCAR_GEN4_PCIE_PHY_0f8 0x0f8
> > > > +#define RCAR_GEN4_PCIE_PHY_148 0x148
> > > > +#define RCAR_GEN4_PCIE_PHY_1d4 0x1d4
> > > > +#define RCAR_GEN4_PCIE_PHY_514 0x514
> > > > +#define RCAR_GEN4_PCIE_PHY_700 0x700
> > > > +
> > >
> > > As I said before, these defines provide no information about the registers at
> > > all. So please use the offset directly and add a comment.
> >
> > I got it.
> >
> > > > #define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> > > > #define RCAR_MAX_LINK_SPEED 4
> > > >
> > > > #define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
> > > > #define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
> > > >
> > > > +#define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin"
> > > > +#define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc000
> > > > +
> > > > +MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);
> > > > +
> > > > struct rcar_gen4_pcie;
> > > > struct rcar_gen4_pcie_drvdata {
> > > > + void (*additional_common_init)(struct rcar_gen4_pcie *rcar);
> > >
> > > What is this init for? Controller? PHY?
> >
> > This init is for controller.
> >
>
> Why do you need a callback for this? There is just a single function that is
> used as of now, so please move the contents to rcar_gen4_pcie_common_init().
r8a779g0 requires the settings. But, r8a779f0 doesn't requires the setting.
So, we can not move the contents to rcar_gen4_pcie_common_init().
> > > > int (*ltssm_enable)(struct rcar_gen4_pcie *rcar);
> > > > enum dw_pcie_device_mode mode;
> > > > };
> > > > @@ -57,12 +88,144 @@ struct rcar_gen4_pcie_drvdata {
> > > > struct rcar_gen4_pcie {
> > > > struct dw_pcie dw;
> > > > void __iomem *base;
> > > > + void __iomem *phy_base;
> > > > struct platform_device *pdev;
> > > > const struct rcar_gen4_pcie_drvdata *drvdata;
> > > > };
> > > > #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> > > >
> > > > /* Common */
> > > > +static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,
> > > > + u32 offset, u32 mask, u32 val)
> > > > +{
> > > > + u32 tmp;
> > > > +
> > > > + tmp = readl(rcar->phy_base + offset);
> > > > + tmp &= ~mask;
> > > > + tmp |= val;
> > > > + writel(tmp, rcar->phy_base + offset);
> > > > +}
> > > > +
> > > > +static int rcar_gen4_pcie_reg_check(struct rcar_gen4_pcie *rcar,
> > > > + u32 offset, u32 mask)
> > > > +{
> > > > + struct dw_pcie *dw = &rcar->dw;
> > > > +
> > > > + if (dw_pcie_readl_dbi(dw, offset) & mask)
> > > > + return -EAGAIN;
> > >
> > > What is this function checking actually? It is just a DBI read. Do you expect
> > > these register accesses to fail?
> >
> > This function is checking whether the register's value with mask is zero or not.
> > - If non-zero, return -EAGAIN.
> > - If zero, return 0. (this is expected value.)
> >
> > Perhaps, should I change the function name? For example, rcar_gen4_pcie_reg_test_bit()?
> > According to the datasheet, software needs to write registers again if the register
> > value(s) is(are) not expected value(s).
> >
>
> Well, I was asking under what circumstances the write may result in non-zero
> value?
The current implementation is:
-----
dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);
dw_pcie_writel_dbi(dw, PRTLGC90, data);
if (rcar_gen4_pcie_reg_check(rcar, PRTLGC89, BIT(30)) >= 0)
break;
...
dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);
ret = rcar_gen4_pcie_reg_check(rcar, PRTLGC89, BIT(30));
ret |= rcar_gen4_pcie_reg_check(rcar, PRTLGC90, BIT(0));
if (ret >= 0)
break;
-----
This is from flowchart of the datasheet. Unfortunately, the datasheet doesn't describe detail.
But, I think that I should implement such a code. And, I assume that these registers have a flag
in the bits, so the write may result in non-zero value.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
