Il 16/05/24 11:23, CK Hu (胡俊光) ha scritto:
Hi, Angelo:
On Thu, 2024-05-16 at 10:11 +0200, AngeloGioacchino Del Regno wrote:
Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths
per HW instance (so potentially up to six displays for multi-vdo SoCs).
The MMSYS or VDOSYS is always the first component in the DDP pipeline,
so it only supports an output port with multiple endpoints - where each
endpoint defines the starting point for one of the (currently three)
possible hardware paths.
Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b3c6888c1457..0ef67ca4122b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -93,6 +93,34 @@ properties:
'#reset-cells':
const: 1
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port node. This port connects the MMSYS/VDOSYS output to
+ the first component of one display pipeline, for example one of
+ the available OVL or RDMA blocks.
+ Some MediaTek SoCs support multiple display outputs per MMSYS.
The display pipeline number usually depend on how many display interface. Display interface is in the end of pipeline.
I have never stated that the display pipeline number depends on that.
Plus, the display interface is not described in the mmsys binding: this document
is only saying that mmsys' endpoint is to be connected to a (supported) component
of your choice. Nothing else.
In below case, two RDMA is merged into one pipeline and output to one display interface DP_INTF. This is usually ONE display.
RDMA -+
Merge -> ... -> DP_INTF
RDMA -+
In below case, one RDMA data output to two display interface DSI and DPI. This is usually TWO display with the same content.
+-> DSI
RDMA -> ... -> +
+-> DPI
The actual content of a display is a software capability - if the hardware supports
that, and some MediaTek SoCs do, the connection does not happen at the endpoint of
mmsys, but later.
So the display pipeline number does not depend on the number of first component. It usually depend on the number of display interface.
I sure agree with that, but again, I have *never stated* that the display pipeline
number depends on the number of the first component.
Regards,
CK
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Output to the primary display pipeline
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Output to the secondary display pipeline
+
+ endpoint@2:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Output to the tertiary display pipeline
+
+ oneOf:
+ - required:
+ - endpoint@0
+ - required:
+ - endpoint@1
+ - required:
+ - endpoint@2
+
required:
- compatible
- reg
