The kernel currently requires all harts to have the same value in the
vlenb csr that is present when a hart supports vector. In order to read
this csr, the kernel needs to boot the hart. Adding vlenb to the DT will
allow the kernel to detect the inconsistency early and not waste time
trying to boot harts that it doesn't support.
Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx>
---
The two patches in this series were previously part of a series "riscv:
Support vendor extensions and xtheadvector" but has been factored out
due to a lack of reviews on the thead specific parts so that series will
be updated separately.
---
Charlie Jenkins (1):
riscv: vector: Use vlenb from DT
Conor Dooley (1):
dt-bindings: riscv: cpus: add a vlen register length property
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++
arch/riscv/include/asm/cpufeature.h | 2 +
arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++
arch/riscv/kernel/vector.c | 12 +++++-
4 files changed, 66 insertions(+), 1 deletion(-)
---
base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6
change-id: 20240515-add_vlenb_to_dt-307bb406ecc5
--
- Charlie
