The clock 'sys_pll_div16' is one of the parents of the GEN clock. It is
generated inside the A1 Peripherals clock controller from 'sys_pll' PLL
clock source with a fixed factor.
Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx>
---
drivers/clk/meson/a1-peripherals.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c
index 621af1e6e4b2..56e44299982c 100644
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
@@ -746,14 +746,27 @@ static struct clk_regmap fclk_div2_divn = {
},
};
+static struct clk_fixed_factor sys_pll_div16 = {
+ .mult = 1,
+ .div = 16,
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_pll_div16",
+ .ops = &clk_fixed_factor_ops,
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "sys_pll",
+ },
+ .num_parents = 1,
+ },
+};
+
/*
- * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver,
* the index 4 is the clock measurement source, it's not supported yet
*/
-static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 };
+static u32 gen_table[] = { 0, 1, 2, 3, 5, 6, 7, 8 };
static const struct clk_parent_data gen_parent_data[] = {
{ .fw_name = "xtal", },
{ .hw = &rtc.hw },
+ { .hw = &sys_pll_div16.hw, },
{ .fw_name = "hifi_pll", },
{ .fw_name = "fclk_div2", },
{ .fw_name = "fclk_div3", },
@@ -2024,6 +2037,7 @@ static struct clk_hw *a1_periphs_hw_clks[] = {
[CLKID_DMC_SEL] = &dmc_sel.hw,
[CLKID_DMC_DIV] = &dmc_div.hw,
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
+ [CLKID_SYS_PLL_DIV16] = &sys_pll_div16.hw,
};
/* Convenience table to populate regmap in .probe */
--
2.43.0
