On 12/05/2024 02:47, Samuel Holland wrote:
>
> On 2024-05-07 1:53 AM, Xingyu Wu wrote:
> > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
> > But now PLL0 rate is 1GHz and the cpu frequency loads become
> > 333/500/500/1000MHz in fact.
> >
> > The PLL0 rate should be default set to 1.5GHz and set the cpu_core
> > rate to 500MHz in safe.
>
> Can this be accomplished by instead setting the CLK_SET_RATE_PARENT flag on
> the CPU_CORE clock? That way PLL0 is automatically set when cpufreq tries to
> change the CPU core frequency. Then there is no DT change and no compatibility
> issue.
>
> Regards,
> Samuel
Thanks for your advice. But cpufreq tries to change the CPU core rate and also
the PLL0 rate with the flag of CLK_SET_RATE_PARENT and the PLL0 will be
changed frequently. I think it goes against our intention and the PLL0 rate should
be fixed or rarely changed. This helps to stabilize the system.
Best regards,
Xingyu Wu
>
> > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110
> > SoC")
> > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> > ---
> > .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index 45b58b6f3df8..28981b267de4 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -390,6 +390,12 @@ spi_dev0: spi@0 {
> > };
> > };
> >
> > +&syscrg {
> > + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
> > + <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> > + assigned-clock-rates = <500000000>, <1500000000>; };
> > +
> > &sysgpio {
> > i2c0_pins: i2c0-0 {
> > i2c-pins {
