On Mon, May 13, 2024 at 02:37:20PM +0200, Herve Codina wrote:
> Hi Rob,
>
> On Tue, 7 May 2024 10:28:06 -0500
> Rob Herring <robh@xxxxxxxxxx> wrote:
>
> ...
> > > +examples:
> > > + - |
> > > + interrupt-controller@e00c0120 {
> > > + compatible = "microchip,lan966x-oic";
> > > + reg = <0xe00c0120 0x190>;
> >
> > Looks like this is part of some larger block?
> >
>
> According to the registers information document:
> https://microchip-ung.github.io/lan9662_reginfo/reginfo_LAN9662.html?select=cpu,intr
>
> The interrupt controller is mapped at offset 0x48 (offset in number of
> 32bit words).
> -> Address offset: 0x48 * 4 = 0x120
> -> size: (0x63 + 1) * 4 = 0x190
>
> IMHO, the reg property value looks correct.
What I mean is h/w blocks don't just start at some address with small
alignment. That wouldn't work from a physical design standpoint. The
larger block here is "CPU System Regs". The block as a whole should be
documented, but maybe that ship already sailed.
Also, here you call it the OIC, but the link above calls it the VCore
interrupt controller.
Rob
