Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY driver. Tested-by: Zhengping Zhang <zhengping.zhang@xxxxxxxxxx> Signed-off-by: Lorenzo Bianconi <lorenzo@xxxxxxxxxx> --- .../bindings/phy/airoha,pcie-phy.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml new file mode 100644 index 000000000000..443d7e717296 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,pcie-phy.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha PCIe PHY + +maintainers: + - Lorenzo Bianconi <lorenzo@xxxxxxxxxx> + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,en7581-pcie-phy + + reg: + maxItems: 3 + + reg-names: + items: + - const: csr_2l + - const: pma0 + - const: pma1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + phy@11e80000 { + compatible = "airoha,en7581-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x1fa5a000 0x0 0xfff>, + <0x0 0x1fa5b000 0x0 0xfff>, + <0x0 0x1fa5c000 0x0 0xfff>; + reg-names = "csr_2l", "pma0", "pma1"; + }; + }; -- 2.45.0
