On Fri, May 10, 2024 at 12:08:56PM +0300, Dmitry Rokosov wrote: > The 'sys_pll_div16' input clock is used as one of the sources for the > GEN clock. > > Signed-off-by: Dmitry Rokosov <ddrokosov@xxxxxxxxxxxxxxxxx> Provided that this new clock is optional in the driver, Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Cheers, Conor. > --- > .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > index 6d84cee1bd75..11862746ba44 100644 > --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml > @@ -30,6 +30,7 @@ properties: > - description: input fixed pll div7 > - description: input hifi pll > - description: input oscillator (usually at 24MHz) > + - description: input sys pll div16 > > clock-names: > items: > @@ -39,6 +40,7 @@ properties: > - const: fclk_div7 > - const: hifi_pll > - const: xtal > + - const: sys_pll_div16 > > required: > - compatible > @@ -65,9 +67,10 @@ examples: > <&clkc_pll CLKID_FCLK_DIV5>, > <&clkc_pll CLKID_FCLK_DIV7>, > <&clkc_pll CLKID_HIFI_PLL>, > - <&xtal>; > + <&xtal>, > + <&clkc_pll CLKID_SYS_PLL_DIV16>; > clock-names = "fclk_div2", "fclk_div3", > "fclk_div5", "fclk_div7", > - "hifi_pll", "xtal"; > + "hifi_pll", "xtal", "sys_pll_div16"; > }; > }; > -- > 2.43.0 > >
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