On Thu, May 09, 2024 at 10:47:46PM +0200, Christian Marangi wrote: > Document brcm,bmips-cbr-reg property. > > Some SoC suffer from a BUG where CBR(Core Base Register) > address might badly/never inizialized by the Bootloader or > reaching it from co-processor registers if the system > boots from secondary CPU results in invalid address. > > The CBR address is always the same on the SoC. > > Usage of this property is to give an address also in these broken > configuration/bootloader. > > Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx> > --- > .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml > index 975945ca2888..6b961b62aff2 100644 > --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml > +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml > @@ -55,6 +55,16 @@ properties: > under the "cpus" node. > $ref: /schemas/types.yaml#/definitions/uint32 > > + brcm,bmips-cbr-reg: > + description: Reference address of the CBR. > + Some SoC suffer from a BUG where CBR(Core Base Register) > + address might badly/never inizialized by the Bootloader or "be badly or never initialized" > + reaching it from co-processor registers if the system "reading"? Otherwise, Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Cheers, Conor. > + boots from secondary CPU results in invalid address. > + The CBR address is always the same on the SoC hence it > + can be provided in DT to handle these broken case. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > patternProperties: > "^cpu@[0-9]$": > type: object > @@ -64,6 +74,20 @@ properties: > required: > - mips-hpt-frequency > > +if: > + properties: > + compatible: > + contains: > + enum: > + - brcm,bcm6358 > + - brcm,bcm6368 > + > +then: > + properties: > + cpus: > + required: > + - brcm,bmips-cbr-reg > + > additionalProperties: true > > examples: > -- > 2.43.0 >
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