On 29/04/2024 15:09, Ravi Gunasekaran wrote:
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
>
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@xxxxxx>
> ---
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 58 +++++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-serdes.h | 7 +++
> 2 files changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..ddb4f1f0d92d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
> /dts-v1/;
>
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
> #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j722s-evm", "ti,j722s";
> @@ -20,6 +22,8 @@
> serial2 = &main_uart0;
> mmc0 = &sdhci0;
> mmc1 = &sdhci1;
> + usb0 = &usb0;
> + usb1 = &usb1;
> };
>
> chosen {
> @@ -202,6 +206,12 @@
> J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
> >;
> };
> +
> + main_usb1_pins_default: main-usb1-default-pins {
> + pinctrl-single,pins = <
> + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> + >;
> + };
> };
>
> &cpsw3g {
> @@ -301,6 +311,14 @@
> "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
> "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
> "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> + p05-hog {
> + /* P05 - USB2.0_MUX_SEL */
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_LOW>;
> + output-high;
> + line-name = "USB2.0_MUX_SEL";
This line-name is already added in gpio-line-names property above.
Do we really need to add it again?
> + };
> };
> };
>
> @@ -384,3 +402,43 @@
> status = "okay";
> bootph-all;
> };
> +
> +&serdes0_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>,
> + <J722S_SERDES1_LANE0_PCIE0_LANE0>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usbss1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb1_pins_default>;
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> index a011ad893b44..9082abeddcb1 100644
> --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -201,4 +201,11 @@
> #define J784S4_SERDES4_LANE3_USB 0x2
> #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
>
> +/* J722S */
> +#define J722S_SERDES0_LANE0_USB 0x0
> +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
> +
> +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
> +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
> +
> #endif /* DTS_ARM64_TI_K3_SERDES_H */
--
cheers,
-roger
