The InnoSilicon DPHY found in RK3128 SoCs supports DSI/LVDS/TTL with a maximum transfer rate of 1 Gbps per lane. While at it also add the newly exported PCLK_MIPIPHY clock id to RK3128_PD_VIO powerdomain as the phy is part of it. Signed-off-by: Alex Bee <knaerzche@xxxxxxxxx> --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..d16a9d03ba2b 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,7 @@ power-domain@RK3128_PD_VIO { <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -496,6 +497,18 @@ hdmi_out: port@1 { }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + power-domains = <&power RK3128_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; -- 2.43.2