Re: [PATCH 5/6] mips: bmips: enable RAC on BMIPS4350

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On 5/3/24 06:54, Christian Marangi wrote:
From: Daniel González Cabanelas <dgcbueu@xxxxxxxxx>

The data RAC is left disabled by the bootloader in some SoCs, at least in
the core it boots from.
Enabling this feature increases the performance up to +30% depending on the
task.

Signed-off-by: Daniel González Cabanelas <dgcbueu@xxxxxxxxx>
Signed-off-by: Álvaro Fernández Rojas <noltari@xxxxxxxxx>
[ rework code and reduce code duplication ]
Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
---
  arch/mips/kernel/smp-bmips.c | 12 ++++++++++++
  1 file changed, 12 insertions(+)

diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 6048c471b5ee..7bde6bbaa41f 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -617,6 +617,18 @@ void bmips_cpu_setup(void)
  		__raw_readl(bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE);
  		break;
+ case CPU_BMIPS4350:
+		u32 rac_addr = BMIPS_RAC_CONFIG_1;
+
+		if (!(read_c0_brcm_cmt_local() & (1 << 31)))
+			rac_addr = BMIPS_RAC_CONFIG;
+
+		/* Enable data RAC */
+		cfg = __raw_readl(bmips_cbr_addr + rac_addr);
+		__raw_writel(cfg | 0xa, bmips_cbr_addr + rac_addr);

This enables data pre-fetching (bit 3) and data-caching (bit 1), have you tried with 0xF to see if this provides any additional speed-up?

Looks correct to me otherwise, I wonder if a flush would be in order right after enabling, though I did not see any specific instructions towards that part in the programming notes.

+		__raw_readl(bmips_cbr_addr + rac_addr);
+		break;
+
  	case CPU_BMIPS4380:
  		/* CBG workaround for early BMIPS4380 CPUs */
  		switch (read_c0_prid()) {

--
Florian

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