> Subject: Re: [PATCH v4 2/3] arm64: dts: freescale: add i.MX95 basic dtsi > > On Fri, May 03, 2024 at 09:37:12AM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@xxxxxxx> > > > > i.MX95 features 6 A55 Cores, ARM Mali GPU, ISP, ML acceleration NPU, > > and Edgelock secure enclave security. This patch is to add a minimal > > dtsi, with cpu cores, coresight, scmi, gic, uart, mu, sdhc, lpi2c added. > > .... > > + }; > > + > > + sram1: sram@20480000 { > > + compatible = "mmio-sram"; > > + reg = <0x0 0x204c0000 0x0 0x18000>; > > + ranges = <0x0 0x0 0x204c0000 0x18000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; > > looks like it need general node name in > https://github.com/devicetree-org/devicetree- > specification/releases/download/v0.4/devicetree-specification-v0.4.pdf > section 2.2.2 > > look like should be "sram-controller", please also check other node name to > match spec. But this is not controller, it is just a piece of on chip memory. Thanks, Peng. > > Frank > > > + > > + firmware { > > + scmi { > > + compatible = "arm,scmi"; > > + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; > > + shmem = <&scmi_buf0>, <&scmi_buf1>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + scmi_devpd: protocol@11 { > > + reg = <0x11>; > > + #power-domain-cells = <1>; > > + }; > > + > > + scmi_perf: protocol@13 { > > + reg = <0x13>; > > + #power-domain-cells = <1>; > > + }; > > + > > + scmi_clk: protocol@14 { > > + reg = <0x14>; > > + #clock-cells = <1>; > > + }; > > + > > + scmi_sensor: protocol@15 { > > + reg = <0x15>; > > + #thermal-sensor-cells = <1>; > > + }; > > + }; > > + }; > > + > > + pmu { > > + compatible = "arm,cortex-a55-pmu"; > > + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > + > > + thermal-zones { > > + a55-thermal { > > + polling-delay-passive = <250>; > > + polling-delay = <2000>; > > + thermal-sensors = <&scmi_sensor 1>; > > + > > + trips { > > + cpu_alert0: trip0 { > > + temperature = <85000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > + > > + cpu_crit0: trip1 { > > + temperature = <95000>; > > + hysteresis = <2000>; > > + type = "critical"; > > + }; > > + }; > > + > > + cooling-maps { > > + map0 { > > + trip = <&cpu_alert0>; > > + cooling-device = > > + <&A55_0 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A55_1 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A55_2 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A55_3 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A55_4 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A55_5 > THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > + }; > > + }; > > + }; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <24000000>; > > + arm,no-tick-in-suspend; > > + interrupt-parent = <&gic>; > > + }; > > + > > + gic: interrupt-controller@48000000 { > > + compatible = "arm,gic-v3"; > > + reg = <0 0x48000000 0 0x10000>, > > + <0 0x48060000 0 0xc0000>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-parent = <&gic>; > > + dma-noncoherent; > > + ranges; > > + > > + its: msi-controller@48040000 { > > + compatible = "arm,gic-v3-its"; > > + reg = <0 0x48040000 0 0x20000>; > > + msi-controller; > > + #msi-cells = <1>; > > + dma-noncoherent; > > + }; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + aips2: bus@42000000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0x0 0x42000000 0x0 0x800000>; > > + ranges = <0x42000000 0x0 0x42000000 > 0x8000000>, > > + <0x28000000 0x0 0x28000000 > 0x10000000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + mu7: mailbox@42430000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x42430000 0x10000>; > > + interrupts = <GIC_SPI 234 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + wdog3: watchdog@42490000 { > > + compatible = "fsl,imx93-wdt"; > > + reg = <0x42490000 0x10000>; > > + interrupts = <GIC_SPI 77 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + timeout-sec = <40>; > > + status = "disabled"; > > + }; > > + > > + tpm3: pwm@424e0000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x424e0000 0x1000>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + tpm4: pwm@424f0000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x424f0000 0x1000>; > > + clocks = <&scmi_clk IMX95_CLK_TPM4>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + tpm5: pwm@42500000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x42500000 0x1000>; > > + clocks = <&scmi_clk IMX95_CLK_TPM5>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + tpm6: pwm@42510000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x42510000 0x1000>; > > + clocks = <&scmi_clk IMX95_CLK_TPM6>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + lpi2c3: i2c@42530000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x42530000 0x10000>; > > + interrupts = <GIC_SPI 58 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C3>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c4: i2c@42540000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x42540000 0x10000>; > > + interrupts = <GIC_SPI 59 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C4>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi3: spi@42550000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x42550000 0x10000>; > > + interrupts = <GIC_SPI 61 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI3>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi4: spi@42560000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x42560000 0x10000>; > > + interrupts = <GIC_SPI 62 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI4>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart3: serial@42570000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42570000 0x1000>; > > + interrupts = <GIC_SPI 64 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART3>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart4: serial@42580000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42580000 0x1000>; > > + interrupts = <GIC_SPI 65 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART4>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart5: serial@42590000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42590000 0x1000>; > > + interrupts = <GIC_SPI 66 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART5>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart6: serial@425a0000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x425a0000 0x1000>; > > + interrupts = <GIC_SPI 67 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART6>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart7: serial@42690000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x42690000 0x1000>; > > + interrupts = <GIC_SPI 68 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART7>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart8: serial@426a0000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x426a0000 0x1000>; > > + interrupts = <GIC_SPI 69 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART8>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c5: i2c@426b0000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x426b0000 0x10000>; > > + interrupts = <GIC_SPI 181 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C5>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c6: i2c@426c0000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x426c0000 0x10000>; > > + interrupts = <GIC_SPI 182 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C6>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c7: i2c@426d0000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x426d0000 0x10000>; > > + interrupts = <GIC_SPI 183 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C7>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c8: i2c@426e0000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x426e0000 0x10000>; > > + interrupts = <GIC_SPI 184 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C8>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi5: spi@426f0000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x426f0000 0x10000>; > > + interrupts = <GIC_SPI 177 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI5>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi6: spi@42700000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x42700000 0x10000>; > > + interrupts = <GIC_SPI 178 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI6>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi7: spi@42710000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x42710000 0x10000>; > > + interrupts = <GIC_SPI 179 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI7>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi8: spi@42720000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x42720000 0x10000>; > > + interrupts = <GIC_SPI 180 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI8>, > > + <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + mu8: mailbox@42730000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x42730000 0x10000>; > > + interrupts = <GIC_SPI 235 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + }; > > + > > + aips3: bus@42800000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0 0x42800000 0 0x800000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x42800000 0x0 0x42800000 0x800000>; > > + > > + usdhc1: mmc@42850000 { > > + compatible = "fsl,imx95-usdhc", > "fsl,imx8mm-usdhc"; > > + reg = <0x42850000 0x10000>; > > + interrupts = <GIC_SPI 86 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk > IMX95_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX95_CLK_USDHC1>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clocks = <&scmi_clk > IMX95_CLK_USDHC1>; > > + assigned-clock-parents = <&scmi_clk > IMX95_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <400000000>; > > + bus-width = <8>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step= <2>; > > + status = "disabled"; > > + }; > > + > > + usdhc2: mmc@42860000 { > > + compatible = "fsl,imx95-usdhc", > "fsl,imx8mm-usdhc"; > > + reg = <0x42860000 0x10000>; > > + interrupts = <GIC_SPI 87 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk > IMX95_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX95_CLK_USDHC2>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clocks = <&scmi_clk > IMX95_CLK_USDHC2>; > > + assigned-clock-parents = <&scmi_clk > IMX95_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <400000000>; > > + bus-width = <4>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step= <2>; > > + status = "disabled"; > > + }; > > + > > + usdhc3: mmc@428b0000 { > > + compatible = "fsl,imx95-usdhc", > "fsl,imx8mm-usdhc"; > > + reg = <0x428b0000 0x10000>; > > + interrupts = <GIC_SPI 191 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk > IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk > IMX95_CLK_WAKEUPAXI>, > > + <&scmi_clk IMX95_CLK_USDHC3>; > > + clock-names = "ipg", "ahb", "per"; > > + assigned-clock-parents = <&scmi_clk > IMX95_CLK_SYSPLL1_PFD1>; > > + assigned-clock-rates = <400000000>; > > + bus-width = <4>; > > + fsl,tuning-start-tap = <1>; > > + fsl,tuning-step= <2>; > > + status = "disabled"; > > + }; > > + }; > > + > > + gpio2: gpio@43810000 { > > + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43810000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX95_CLK_BUSWAKEUP>; > > + clock-names = "gpio", "port"; > > + }; > > + > > + gpio3: gpio@43820000 { > > + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43820000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX95_CLK_BUSWAKEUP>; > > + clock-names = "gpio", "port"; > > + }; > > + > > + gpio4: gpio@43840000 { > > + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43840000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX95_CLK_BUSWAKEUP>; > > + clock-names = "gpio", "port"; > > + }; > > + > > + gpio5: gpio@43850000 { > > + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x43850000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, > > + <&scmi_clk IMX95_CLK_BUSWAKEUP>; > > + clock-names = "gpio", "port"; > > + }; > > + > > + aips1: bus@44000000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0x0 0x44000000 0x0 0x800000>; > > + ranges = <0x44000000 0x0 0x44000000 0x800000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + mu1: mailbox@44220000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x44220000 0x10000>; > > + interrupts = <GIC_SPI 224 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_BUSAON>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + tpm1: pwm@44310000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x44310000 0x1000>; > > + clocks = <&scmi_clk IMX95_CLK_BUSAON>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + tpm2: pwm@44320000 { > > + compatible = "fsl,imx7ulp-pwm"; > > + reg = <0x44320000 0x1000>; > > + clocks = <&scmi_clk IMX95_CLK_TPM2>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + > > + lpi2c1: i2c@44340000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x44340000 0x10000>; > > + interrupts = <GIC_SPI 13 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C1>, > > + <&scmi_clk IMX95_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpi2c2: i2c@44350000 { > > + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp- > lpi2c"; > > + reg = <0x44350000 0x10000>; > > + interrupts = <GIC_SPI 14 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPI2C2>, > > + <&scmi_clk IMX95_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi1: spi@44360000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x44360000 0x10000>; > > + interrupts = <GIC_SPI 16 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI1>, > > + <&scmi_clk IMX95_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpspi2: spi@44370000 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "fsl,imx95-spi", "fsl,imx7ulp- > spi"; > > + reg = <0x44370000 0x10000>; > > + interrupts = <GIC_SPI 17 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPSPI2>, > > + <&scmi_clk IMX95_CLK_BUSAON>; > > + clock-names = "per", "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart1: serial@44380000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x44380000 0x1000>; > > + interrupts = <GIC_SPI 19 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART1>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + lpuart2: serial@44390000 { > > + compatible = "fsl,imx95-lpuart", > "fsl,imx8ulp-lpuart", > > + "fsl,imx7ulp-lpuart"; > > + reg = <0x44390000 0x1000>; > > + interrupts = <GIC_SPI 20 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_LPUART2>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + adc1: adc@44530000 { > > + compatible = "nxp,imx93-adc"; > > + reg = <0x44530000 0x10000>; > > + interrupts = <GIC_SPI 199 > IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 200 > IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 201 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_ADC>; > > + clock-names = "ipg"; > > + status = "disabled"; > > + }; > > + > > + mu2: mailbox@445b0000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x445b0000 0x1000>; > > + ranges; > > + interrupts = <GIC_SPI 226 > IRQ_TYPE_LEVEL_HIGH>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + #mbox-cells = <2>; > > + > > + sram0: sram@445b1000 { > > + compatible = "mmio-sram"; > > + reg = <0x445b1000 0x400>; > > + ranges = <0x0 0x445b1000 0x400>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + scmi_buf0: scmi-sram-section@0 { > > + compatible = "arm,scmi- > shmem"; > > + reg = <0x0 0x80>; > > + }; > > + > > + scmi_buf1: scmi-sram-section@80 > { > > + compatible = "arm,scmi- > shmem"; > > + reg = <0x80 0x80>; > > + }; > > + }; > > + > > + }; > > + > > + mu3: mailbox@445d0000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x445d0000 0x10000>; > > + interrupts = <GIC_SPI 228 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_BUSAON>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu4: mailbox@445f0000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x445f0000 0x10000>; > > + interrupts = <GIC_SPI 230 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_BUSAON>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + mu6: mailbox@44630000 { > > + compatible = "fsl,imx95-mu"; > > + reg = <0x44630000 0x10000>; > > + interrupts = <GIC_SPI 206 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk IMX95_CLK_BUSAON>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + }; > > + > > + mailbox@47320000 { > > + compatible = "fsl,imx95-mu-v2x"; > > + reg = <0x0 0x47320000 0x0 0x10000>; > > + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + }; > > + > > + mailbox@47350000 { > > + compatible = "fsl,imx95-mu-v2x"; > > + reg = <0x0 0x47350000 0x0 0x10000>; > > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + }; > > + > > + /* GPIO1 is under exclusive control of System Manager */ > > + gpio1: gpio@47400000 { > > + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; > > + reg = <0x0 0x47400000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&scmi_clk IMX95_CLK_M33>, > > + <&scmi_clk IMX95_CLK_M33>; > > + clock-names = "gpio", "port"; > > + status = "disabled"; > > + }; > > + > > + elemu0: mailbox@47520000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47520000 0x0 0x10000>; > > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + elemu1: mailbox@47530000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47530000 0x0 0x10000>; > > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + elemu2: mailbox@47540000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47540000 0x0 0x10000>; > > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + elemu3: mailbox@47550000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47550000 0x0 0x10000>; > > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + }; > > + > > + elemu4: mailbox@47560000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47560000 0x0 0x10000>; > > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + elemu5: mailbox@47570000 { > > + compatible = "fsl,imx95-mu-ele"; > > + reg = <0x0 0x47570000 0x0 0x10000>; > > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > > + #mbox-cells = <2>; > > + status = "disabled"; > > + }; > > + > > + aips4: bus@49000000 { > > + compatible = "fsl,aips-bus", "simple-bus"; > > + reg = <0x0 0x49000000 0x0 0x800000>; > > + ranges = <0x49000000 0x0 0x49000000 0x800000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + smmu: iommu@490d0000 { > > + compatible = "arm,smmu-v3"; > > + reg = <0x490d0000 0x100000>; > > + interrupts = <GIC_SPI 325 > IRQ_TYPE_EDGE_RISING>, > > + <GIC_SPI 328 > IRQ_TYPE_EDGE_RISING>, > > + <GIC_SPI 334 > IRQ_TYPE_EDGE_RISING>, > > + <GIC_SPI 326 > IRQ_TYPE_EDGE_RISING>; > > + interrupt-names = "eventq", "gerror", "priq", > "cmdq-sync"; > > + #iommu-cells = <1>; > > + status = "disabled"; > > + }; > > + }; > > + }; > > +}; > > > > -- > > 2.37.1 > >