Hi,
On Wed, Jan 31, 2024 at 03:59:15PM +0300, Aleksandr Shubin wrote:
> + if (state->polarity != pwm->state.polarity ||
> + state->duty_cycle != pwm->state.duty_cycle ||
> + state->period != pwm->state.period) {
> + ctl = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm));
> + clk_cfg = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm));
> + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc);
> + bus_rate = clk_get_rate(sun20i_chip->clk_apb0);
> + if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) {
> + /* if the neighbor channel is enable, check period only */
> + use_bus_clk = FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) != 0;
> + val = mul_u64_u64_div_u64(state->period,
> + (use_bus_clk ? bus_rate : hosc_rate),
> + NSEC_PER_SEC);
> +
> + div_m = FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg);
> + } else {
> + /* check period and select clock source */
> + use_bus_clk = false;
> + val = mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC);
> + if (val <= 1) {
> + use_bus_clk = true;
> + val = mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC);
> + if (val <= 1) {
> + ret = -EINVAL;
> + goto unlock_mutex;
> + }
> + }
> + div_m = fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC));
> + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) {
> + ret = -EINVAL;
> + goto unlock_mutex;
> + }
> +
> + /* set up the CLK_DIV_M and clock CLK_SRC */
> + clk_cfg = FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m);
> + clk_cfg |= FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk);
> +
> + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm));
> + }
If I'm reading this correctly, for each PWM pair you set the clock once.
Wouldn't this mean that the order of setting PWMs would affect the accuracy?
It would be good to note this down perhaps?
John.
> --
> 2.25.1
>
>
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