On Sun, 28 Apr 2024 13:40:35 +0200 Dragan Simic <dsimic@xxxxxxxxxxx> wrote: Hi, thanks for taking care of this! > Add missing cache information to the Allwinner A64 SoC dtsi, to allow > the userspace, which includes lscpu(1) that uses the virtual files provided > by the kernel under the /sys/devices/system/cpu directory, to display the > proper A64 cache information. > > While there, use a more self-descriptive label for the L2 cache node, which > also makes it more consistent with other SoC dtsi files. > > The cache parameters for the A64 dtsi were obtained and partially derived > by hand from the cache size and layout specifications found in the following > datasheets and technical reference manuals: > > - Allwinner A64 datasheet, version 1.1 > - ARM Cortex-A53 revision r0p3 TRM, version E > > For future reference, here's a brief summary of the documentation: > > - All caches employ the 64-byte cache line length > - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction > cache and 32 KB of L1 4-way, set-associative data cache > - The entire SoC has 512 KB of unified L2 16-way, set-associative cache So that looks correct when checking the manuals, and the per-CPU entries below match both between themselves and with that description above. However I have some level of distrust towards the Allwinner manuals, regarding the cache sizes (which are chosen by Allwinner). So while I haven't measured this myself, nor checked the cache type registers, tinymembench's memory latency test supports those sizes are correct: https://github.com/ssvb/tinymembench/wiki/PINE64-(Allwinner-A64) > Signed-off-by: Dragan Simic <dsimic@xxxxxxxxxxx> Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx> Cheers, Andre > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 ++++++++++++++++--- > 1 file changed, 32 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index 57ac18738c99..86074d03afa9 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -51,49 +51,76 @@ cpu0: cpu@0 { > device_type = "cpu"; > reg = <0>; > enable-method = "psci"; > - next-level-cache = <&L2>; > clocks = <&ccu CLK_CPUX>; > clock-names = "cpu"; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache>; > }; > > cpu1: cpu@1 { > compatible = "arm,cortex-a53"; > device_type = "cpu"; > reg = <1>; > enable-method = "psci"; > - next-level-cache = <&L2>; > clocks = <&ccu CLK_CPUX>; > clock-names = "cpu"; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache>; > }; > > cpu2: cpu@2 { > compatible = "arm,cortex-a53"; > device_type = "cpu"; > reg = <2>; > enable-method = "psci"; > - next-level-cache = <&L2>; > clocks = <&ccu CLK_CPUX>; > clock-names = "cpu"; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache>; > }; > > cpu3: cpu@3 { > compatible = "arm,cortex-a53"; > device_type = "cpu"; > reg = <3>; > enable-method = "psci"; > - next-level-cache = <&L2>; > clocks = <&ccu CLK_CPUX>; > clock-names = "cpu"; > #cooling-cells = <2>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache>; > }; > > - L2: l2-cache { > + l2_cache: l2-cache { > compatible = "cache"; > cache-level = <2>; > cache-unified; > + cache-size = <0x80000>; > + cache-line-size = <64>; > + cache-sets = <512>; > }; > }; > >
