On 4/23/24 2:30 PM, MD Danish Anwar wrote: > Add device tree overlay to enable both ICSSG1 ports available on AM64x-EVM > in MII mode. > > Signed-off-by: MD Danish Anwar <danishanwar@xxxxxx> > --- > NOTE: This patch depends on [1]. Without [1] mii mode will not work for > ICSSG. Patch [1] is currently posted to net subsystem. > > This patch is based on next-20240423 linux-next tag. > > [1] https://lore.kernel.org/all/20240423084828.1309294-1-danishanwar@xxxxxx/ > > arch/arm64/boot/dts/ti/Makefile | 4 + > .../ti/k3-am642-evm-icssg1-dualemac-mii.dtso | 101 ++++++++++++++++++ > 2 files changed, 105 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso > [...] > diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso > new file mode 100644 > index 000000000000..3081b5c64886 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac-mii.dtso > @@ -0,0 +1,101 @@ > +// SPDX-License-Identifier: GPL-2.0 Please update the license to "GPL-2.0-only OR MIT" > +/** > + * DT overlay for enabling both ICSSG1 port on AM642 EVM in MII mode > + * > + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +/dts-v1/; > +/plugin/; > +#include <dt-bindings/gpio/gpio.h> > +#include "k3-pinctrl.h" > + > +&{/} { > + aliases { > + ethernet1 = "/icssg1-eth/ethernet-ports/port@1"; > + }; > + > + mdio-mux-2 { > + compatible = "mdio-mux-multiplexer"; > + mux-controls = <&mdio_mux>; > + mdio-parent-bus = <&icssg1_mdio>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + mdio@0 { > + reg = <0x0>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + icssg1_phy2: ethernet-phy@3 { > + reg = <3>; > + }; > + }; > + }; > +}; > + > +&main_pmx0 { > + icssg1_mii1_pins_default: icssg1-mii1-default-pins { > + pinctrl-single,pins = < > + AM64X_IOPAD(0x00f8, PIN_INPUT, 1) /* (V9) PRG1_PRU0_GPO16.PR1_MII_MT0_CLK */ > + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y9) PRG1_PRU0_GPO15.PR1_MII0_TXEN */ > + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA9) PRG1_PRU0_GPO14.PR1_MII0_TXD3 */ > + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (W9) PRG1_PRU0_GPO13.PR1_MII0_TXD2 */ > + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (U9) PRG1_PRU0_GPO12.PR1_MII0_TXD1 */ > + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA8) PRG1_PRU0_GPO11.PR1_MII0_TXD0 */ > + AM64X_IOPAD(0x00c8, PIN_INPUT, 1) /* (Y8) PRG1_PRU0_GPO4.PR1_MII0_RXDV */ > + AM64X_IOPAD(0x00d0, PIN_INPUT, 1) /* (AA7) PRG1_PRU0_GPO6.PR1_MII_MR0_CLK */ > + AM64X_IOPAD(0x00c4, PIN_INPUT, 1) /* (V8) PRG1_PRU0_GPO3.PR1_MII0_RXD3 */ > + AM64X_IOPAD(0x00c0, PIN_INPUT, 1) /* (W8) PRG1_PRU0_GPO2.PR1_MII0_RXD2 */ > + AM64X_IOPAD(0x00cc, PIN_INPUT, 1) /* (V13) PRG1_PRU0_GPO5.PR1_MII0_RXER */ > + AM64X_IOPAD(0x00bc, PIN_INPUT, 1) /* (U8) PRG1_PRU0_GPO1.PR1_MII0_RXD1 */ > + AM64X_IOPAD(0x00b8, PIN_INPUT, 1) /* (Y7) PRG1_PRU0_GPO0.PR1_MII0_RXD0 */ > + AM64X_IOPAD(0x00d8, PIN_INPUT, 1) /* (W13) PRG1_PRU0_GPO8.PR1_MII0_RXLINK */ > + >; > + }; > + > + icssg1_mii2_pins_default: icssg1-mii2-default-pins { > + pinctrl-single,pins = < > + AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */ > + AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */ > + AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */ > + AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */ > + AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */ > + AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */ > + AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */ > + AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */ > + AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */ > + AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */ > + AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */ > + AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */ > + AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */ > + AM64X_IOPAD(0x0128, PIN_INPUT, 1) /* (U12) PRG1_PRU1_GPO8.PR1_MII1_RXLINK */ > + >; > + }; > +}; > + > +&cpsw3g { > + pinctrl-0 = <&rgmii1_pins_default>; > +}; > + > +&cpsw_port2 { > + status = "disabled"; > +}; > + > +&mdio_mux_1 { > + status = "disabled"; > +}; > + > +&icssg1_eth { > + pinctrl-0 = <&icssg1_mii1_pins_default &icssg1_mii2_pins_default>; > +}; > + > +&icssg1_emac0 { > + phy-mode = "mii"; > +}; > + > +&icssg1_emac1 { > + status = "okay"; > + phy-handle = <&icssg1_phy2>; > + phy-mode = "mii"; > +}; -- Regards, Ravi
