The USB phy of Sophgo CV18XX series SoC needs to sense a pin called "VBUS_DET" to get the right operation mode. If this pin is not connected, it only supports setting the mode manually. Add USB phy bindings for Sophgo CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx> --- .../bindings/phy/sophgo,cv1800-usb-phy.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml new file mode 100644 index 000000000000..7e3382c18d44 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/sophgo,cv1800-usb-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/sophgo,cv1800-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV18XX/SG200X USB 2.0 PHY + +maintainers: + - Inochi Amaoto <inochiama@xxxxxxxxxxx> + +properties: + compatible: + const: sophgo,cv1800-usb-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY clock + - description: PHY app clock + - description: PHY stb clock + - description: PHY lpm clock + + clock-names: + items: + - const: phy + - const: app + - const: stb + - const: lpm + + vbus_det-gpios: + description: GPIO to the USB OTG VBUS detect pin. This should not be + defined if vbus_det pin and switch pin are connected, which may + break the VBUS detection. + maxItems: 1 + + sophgo,switch-gpios: + description: GPIO array for the phy to control connected switch. For + host mode, the driver will set these GPIOs to low one by one. For + device mode, the driver will set these GPIOs to high in reverse + order. + maxItems: 2 + +required: + - compatible + - "#phy-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + phy@48 { + compatible = "sophgo,cv1800-usb-phy"; + reg = <0x48 0x4>; + #phy-cells = <0>; + clocks = <&clk 92>, <&clk 93>, + <&clk 94>, <&clk 95>; + clock-names = "phy", "app", "stb", "lpm"; + }; + +... -- 2.44.0
